參數(shù)資料
型號(hào)： VNC1L-1A
廠商： Future Technology Devices International Ltd
元件分類： 總線控制器
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, GREEN, LQFP-48
文件頁數(shù)： 13/32頁
文件大?。?/td> 672K
代理商： VNC1L-1A
Copyright 2009 Future Technology Devices International Limited
20
Document Reference No.: FT_000030
Vinculum VNC1L Embedded USB Host Controller IC Datasheet Version 2.02
Clearance No.: FTDI# 50
Figure 5.6 SPI Slave Mode Status Read
5.3 Parallel FIFO Interface
When VNC1L data and control buses are configured in the parallel FIFO interface mode, then it is
functionally equivalent to FTDI FT245R and FT245B devices.
5.3.1 Signal Descriptions
The Parallel FIFO interface signals are described in Table 5.9.
Pin No.
Name
Type
Description
31
D0
I/O
FIFO Data Bus Bit 0
32
D1
I/O
FIFO Data Bus Bit 1
33
D2
I/O
FIFO Data Bus Bit 2
34
D3
I/O
FIFO Data Bus Bit 3
35
D4
I/O
FIFO Data Bus Bit 4
36
D5
I/O
FIFO Data Bus Bit 5
37
D6
I/O
FIFO Data Bus Bit 6
38
D7
I/O
FIFO Data Bus Bit 7
41
RXF#
Output
When high, do not read data from the FIFO.
When low, there is data available in the FIFO which can be read by strobing
RD# low, then high.
42
TXE#
Output
When high, do not write data into the FIFO.
When low, data can be written into the FIFO by strobing WR high, then low.
43
RD#
Input
Enables the current FIFO data byte on D0...D7 when low. Fetches the next FIFO
data byte (if available) from the receive FIFO buffer when RD# goes from high
to low
44
WR
Input
Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR
goes from high to low.
Table 5.9 Data and Control Bus Signal Mode Options - Parallel FIFO Interface
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