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參數(shù)資料
| 型號： | VNC2-64Q1B-REEL |
| 廠商： | FTDI, Future Technology Devices International Ltd |
| 文件頁數(shù)： | 50/88頁 |
| 文件大小： | 0K |
| 描述： | IC USB HOST/DEVICE CTRL 64-QFN |
| 應(yīng)用說明： | Vinculum-II IO Cell Description AppNote Vinculum-II Debug Interface Description AppNote Vinculum-II IO Mux Explained AppNote Vinculum-II PWM Example AppNote Migrating Vinculum Designs AppNote |
| 特色產(chǎn)品： | Vinculum VNC2 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Vinculum-II |
| 控制器類型： | USB 2.0 控制器 |
| 接口： | USB，主機(jī)/設(shè)備配置，UART，SPI，PWM，閃存 256K，DMA 4CH |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 電流 - 電源： | 25mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（8x8） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 634 (CN2011-ZH PDF) |
| 其它名稱： | 768-1046-6 |
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Copyright 2009-2011 Future Technology Devices International Limited
Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.5
Document No.: FT_000138 Clearance No.: FTDI# 143
64 Pin
Package
Available
pins
48 Pin
Package
Available
pins
32 Pin
Package
Available
pins
Name
Type
Description
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
62
12,16,
21, 32,
36, 42,
46
12, 24,
30
spi_m_mosi
Output
Master Out Slave In
Synchronous data from master to slave
13, 17,
22, 26,
31, 41,
45, 49,
55, 59,
63
13, 18,
22, 33,
37, 43,
47
14, 25,
31
spi_m_miso
Input
Master In Slave Out
Synchronous data from slave to master
14, 18,
23, 27,
32, 42,
46, 50,
56, 60,
64
14, 19,
23, 34,
38, 44,
48
15, 26,
32
spi_m_ss_0#
Output
Active low slave select 0 from master to
slave 0
11, 15,
19, 24,
28, 39,
43, 47,
51, 57,
61
11, 15,
20, 31,
35, 41,
45
11, 23
29
spi_m_ss_1#
Output
Active low slave select 1 from master to
slave 1
Table 6.13 SPI Master Signal Names
The main purpose of the SPI Master block is to transfer data between an external SPI interface and the
VNC2. It does this under the control of the CPU and DMA engine via the on chip I/O bus.
An SPI master interface transfer can only be initiated by the SPI Master and begins with the slave select
signal being asserted. This is followed by a data byte being clocked out with the master supplying SCLK.
The master always supplies the first byte, which is called a command byte. After this the desired number
of data bytes are transferred before the transaction is terminated by the master de-asserting slave
select.
The SPI Master will transmit on MOSI as well as receive on MISO during every data stage. At the end of
each byte spi_tx_done and spi_rx_full_int are set. Figure 6.21 Typical SPI Master Timing and
Table 6.14 SPI Master Timing show an example of this.
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