參數(shù)資料
型號(hào): VNC2-64Q1B-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁(yè)數(shù): 8/88頁(yè)
文件大?。?/td> 0K
描述: IC USB HOST/DEVICE CTRL 64-QFN
應(yīng)用說(shuō)明: Vinculum-II IO Cell Description AppNote
Vinculum-II Debug Interface Description AppNote
Vinculum-II IO Mux Explained AppNote
Vinculum-II PWM Example AppNote
Migrating Vinculum Designs AppNote
特色產(chǎn)品: Vinculum VNC2
標(biāo)準(zhǔn)包裝: 1
系列: Vinculum-II
控制器類(lèi)型: USB 2.0 控制器
接口: USB,主機(jī)/設(shè)備配置,UART,SPI,PWM,閃存 256K,DMA 4CH
電源電壓: 1.62 V ~ 1.98 V
電流 - 電源: 25mA
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 64-QFN(8x8)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 634 (CN2011-ZH PDF)
其它名稱: 768-1046-6
16
Copyright 2009-2011 Future Technology Devices International Limited
Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.5
Document No.: FT_000138 Clearance No.: FTDI# 143
3.10 Pin Configuration USB and Power
Pin No
Name
Type
Description
64 pin
48 pin
32 pin
33
25
17
USB1DP
I/O
USB host/slave port 1 - USB Data Signal Plus with
integrated pull-up/pull-down resistor.
34
26
18
USB1DM
I/O
USB host/slave port 1 - USB Data Signal Minus with
integrated pull-up/pull-down resistor.
36
28
20
USB2DP
I/O
USB host/slave port 2 - USB Data Signal Plus with
integrated pull-up/pull-down resistor.
37
29
21
USB2DM
I/O
USB host/slave port 2 - USB Data Signal Minus with
integrated pull-up/pull-down resistor.
Table 3.1 USB Interface Group
Pin No
Name
Type
Description
64 pin
48 pin
32 pin
1, 30,
35, 53
1, 24,
27, 39
1, 16,
19, 27
GND
PWR
Device ground supply pins.
2
3.3V
VREGIN
PWR
+3.3V supply to the regulator.
3
3*
3
1.8V
VCC PLL
IN
PWR
+1.8V supply to the internal clock multiplier. This pin
requires a 100nF decoupling capacitor.
* 48 pin LQFP package only – This power input is internally
connected to VREG_OUT.
All other packages need this pin connected to a 1.8V power
source. Most common applications will connect this to
VREG_OUT.
6
GND PLL
PWR
Device analogue ground supply for internal clock multiplier.
7
7*
7
VREG
OUT
Output
1.8V output from regulator to device core
* N/C on 48 pin LQFP package only.
All other packackages will typically need to connect pins 7
and 3.
21, 38,
54
17, 30,
40
13, 22,
28
VCCIO
PWR
+3.3V supply to the input / output. Interface pins
(IOBUS). Leaving the VCCIO unconnected will lead to
unpredictable operation on the interface pins.
Table 3.2 Power and Ground
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