VP531E/VP551E
2
66.83
1.050
27k
1.3699
24.93
80
33.75
17.64
1.40
7.62
7.62
0.40
34.15
18.71
8.02
8.02
0.00
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions
DC CHARACTERISTICS
VIN
VIL
VIH
VIL
IIH
IIL
VOH
VOL
VOL
2.0
0.7 VDD
3.7
0.8
0.3 VDD
10
-10
0.4
0.6
V
V
V
V
μ
A
μ
A
V
V
V
Parameter
Conditions
VIN = VDD
VIN = VSS
IOH = -1mA
IOL = +4mA
IOL = +6mA
Symbol
Min.
Typ.
Max.
Units
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions
DC CHARACTERISTICS DACs
INL
DNL
V
REF
Z
R
I
REF
K
DAC
±
1.5
±
1
±
5
LSB
LSB
% grey
μ
A
V
mA
pV-s
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Parameter
Symbol
Min.
Typ.
Max.
Units
Accuracy (each DAC)
Integral linearity error
Diffential linearity error
DAC matching error
Monotonicity
LSB size
Internal reference voltage
Internal reference voltage output impedance
Reference Current (V
REF
/R
REF
) R
REF
= 769
DAC Gain Factor (V
OUT
= K
DAC
x I
REF
x R
L
). V
OUT
= DAC code 511
Peak Glitch Energy (see fig.8)
CVBS (see note), Y and C - NTSC (pedestal enabled)
Maximum output, relative to sync bottom
White level relative to black level
Black level relative to blank level
Blank level relative to sync level
Colour burst peak - peak
DC offset (bottom of sync)
CVBS, Y and C - PAL
Maximum output
White level relative to black level
Black level relative to sync level
Colour burst peak - peak
DC offset (bottom of sync)
Digital Inputs TTL compatible (except SDA, SCL)
Input high voltage
Input low voltage
Digital Inputs SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Digital Outputs CMOS compatible
Output high voltage
Output low voltage
Digital Output SDA
Output low voltage
guaranteed
Note: For the inverted CVBS output subtract the above currents from the maximum output (DAC code 511 = 34.12mA).
All figures are for: R
REF
= 769
, R
L
= 37.5
. When the device is set up in NTSC mode there is a +0.25% error in the PAL levels.
If R
L
= 75
then R
REF
= 1538