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參數(shù)資料
| 型號： | VP531 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | NTSC/PAL Digital Video Encoder |
| 中文描述： | NTSC / PAL數(shù)字視頻編碼器 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 285K |
| 代理商： | VP531 |
VP531E/VP551E
5
Pin Name
PD0-7
Pin No.
39 - 46
Description
8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit, corresponding to Pin
46. These pins are internally pulled low.
8 Bit General Purpose Port input/output. D0 is the least significant bit, corresponding to Pin 3.
These pins are internally pulled low.
27MHz Pixel Clock input. The VP531 internally divides PXCK by two to provide the pixel
clock.
The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of
the BURST pulse, (lines 10-263 and 273-525 for NTSC; lines 6-310 and 319-623 for PAL-
B,D, G,I,N(Argentina)).
Composite sync pulse output. This is an active low output signal.
JTAG Data scan output port.
JTAG Data scan input port.
JTAG Scan select input.
JTAG Scan clock input.
Slave address select.
Slave address select.
Standard I
2
C bus serial clock input.
Standard I
2
C bus serial data input/output.
Master reset. This is an asynchronous active low input signal and must be asserted for a
minimum of 200ns in order to reset the VP531/VP551.
Reference square wave input used only during Genlock mode.
Voltage reference output. This output is nominally 1·055V and should be decoupled with a
100nF capacitor to GND.
DAC full sacle current control. A resistor connected between this pin and GND sets the
magnitude of the video output current. An internal loop amplifier control a reference current
flowing through this resistor so that the voltage across it is equal to the Vref voltage.
DAC compensation. A 100nF ceramic capacitor must be connected between pin 52 and pin
53.
True luminance, true chrominance and inverted composite video signal outputs. These are
high impedance current source outputs. A DC path to GND must exist from each of these
pins
D0-7
3 - 10
PXCK
15
CLAMP
17
COMPSYNC
TDO
TDI
TMS
TCK
SA1
SA2
SCL
SDA
RESET
18
21
22
23
24
26
27
28
30
34
REFSQ
VREF
35
50
DAC GAIN
51
COMP
52
LUMAOUT
COMPOUT
CHROMAOUT
NOT USED
VDD
54
56
58
60, 61, 64
1, 12, 16,
20, 29,
32, 33,
37, 48
53, 59
62, 63
2, 11, 13,
14, 19,
25, 31,
36, 38, 47
49, 55, 57
Positive supply input. All VDD pins must be connected.
AVDD
Analog positive supply input. All AVDD pins must be connected.
GND
Negative supply input. All GND pins must be connected.
AGND
Negative supply input. All AGND pins must be connected.
PIN DESCRIPTIONS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VP5513CG1N | NTSC/PAL Digital Video Encoder |
| VP5513GP1N | NTSC/PAL Digital Video Encoder |
| VP5513 | NTSC/PAL Digital Video Encoder |
| VP5513A1N | NTSC/PAL Digital Video Encoder |
| VP551DCGGP1R | Color Encoder Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP5311ACGGP1R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Encoder Circuit |
| VP5311B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:NTSC/PAL Digital Video Encoder |
| VP5311B/CG/GP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:NTSC/PAL Digital Video Encoder |
| VP5311BCGGP1N | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:NTSC/PAL Digital Video Encoder |
| VP5311C | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:NTSC/PAL Digital Video Encoder |
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