參數(shù)資料
型號: VP5513CG1N
廠商: Zarlink Semiconductor Inc.
英文描述: NTSC/PAL Digital Video Encoder
中文描述: NTSC / PAL數(shù)字視頻編碼器
文件頁數(shù): 15/19頁
文件大?。?/td> 276K
代理商: VP5513CG1N
VP5313/VP5513
14
10.250
μ
s
48 IRE
10.500
μ
s
6.5D (12.910
μ
s)
2.0D (3.972
μ
s)
1.0D (1.986
μ
s)
16.0D (31.778
μ
s)
32.0D (63.556)
0.240
μ
s
50 IRE
0 IRE
0 IRE
48 IRE
50 IRE
10.750
μ
s
0.288
μ
s
52 IRE
2 IRE
52 IRE
Encoder minimum
Encoder nominal
Encoder maximum
Description
H-sync to clock run-in
Clock run-in
2, 3
Clock run-in to third start bit
3
Data bit
1, 3
Data characters
4
Horizontal line
1
Rise / fall time of data bit transitions
5
Data bit high (logic level one)
6
Clock run-in maximum
Data bit low (logic level zero)
6
Clock run-in minimum
Data bit differential (high - low)
Clock run-in differential (max. - min)
Interval
A
B
C
D
E
H
Table. 5 Closed Caption data timing. (source EIA R - 4.3 Sept 16 1992)
Notes
1.
The Horizontal line frequency fH is nominally 15734.26Hz
±
0.05Hz. Interval D shall be adjusted to D = 1/(fH x 32) for the
instantaneous fH at line 21.
The clock run-in signal consists of 7.0 cycles of a 0.5034965MHz (1/D) sine wave when measured from the leading to trailing
0 IRE points. The sine wave is to be symmetrical about the 25 IRE level.
The negative going midpoints (half amplitude) of the clock run-in shall be coherent with the midpoints (half amplitude) of the
Start and Data bit transitions.
Two characters, each consisting of 7 data bits and 1 odd parity bit.
2 T Bar, measured between the 10% and 90% amplitude points.
The clock run-in maximum level shall not differ from the data bit high level by more than
±
1 IRE. The clock run-in minimum
level shall not differ from the data bit low level by more than
±
1 IRE.
2.
3.
4.
5.
6.
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