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參數(shù)資料
| 型號： | VP7615 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Colour Digital Video Camera Decoder IC |
| 中文描述： | 彩色數(shù)碼攝像機解碼器IC |
| 文件頁數(shù)： | 20/26頁 |
| 文件大小： | 302K |
| 代理商： | VP7615 |
19
VP7615
RCLK to output (CPSEL, SDAO, SDMN)
rising edge of CPCKA or CPCKB to output (YY[7..0], UV[7..0],
CLK1, VSYNC, HSYNC,VACT, HACT, BFLAG)
falling edge of CLK2 to output (YY[7..0], UV[7..0], CLK1, VSYNC,
HSYNC, VACT, HACT, BFLAG)
falling edge of CLK1 to output (YY[7..0], UV[7..0],VSYNC, HSYNC,
VACT, HACT, BFLAG)
propagation delay from CPCKA or CPCKB to CK2
propagation delay from INVI to INVO
propagation delay from SCLI to SCLOA or SCLOB
rising edge of OUTEN to outputs tri-state (CLK1, CLK2, VSYNC,
HSYNC, VACT, HACT, BFLAG, FIELD, YY[7:0], UV[7:0])
falling edge of OUTEN to outputs (CLK1, CLK2, VSYNC, HSYNC,
VACT, HACT, BFLAG, FIELD, YY[7:0], UV[7:0])
-2
-3
20
21
7
5
12
11
15
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
fCPX
tCPX
dcCPX
tsuCPDX
thCPDX
fRCK
twRSTN
Description
Name
frequency CPCKA or CPCKB
period CPCKA or CPCKB
duty cycle CPCKA or CPCKB
setup time,
CPDA [3..0] to CPCKA or
CPDB [3..0] to CPCKB
hold time,
CPDA [3..0] to CPCKA or
CPDB [3..0] to CPCKB
frequency RCLK
pulse width of RSTN
Unit
Min.
0
33
40
Max.
30
-
60
MHz
ns
%
ns
ns
MHz
ns
4
4
10
110
33
TIMING REQUIREMENTS
Value
tcqRCLK
tcpCPX
tcqCK2f
tcpCK1f
tpdCK2
tpdINV
tpdSCL
tdis
toen
Description
Name
Unit
Min.
TIMING CHARACTERISTICS
Value
Max.
HACT
VACT
FIELD
VSYNC
H
3.0H
Fig.8 Odd Field Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VP7615CGFP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Colour Digital Video Camera Decoder IC |
| VP-7710V-36001 | 制造商:Via Technologies, Inc 功能描述:- Bulk |
| VP-7710V-36121 | 制造商:VIA Technologies Inc 功能描述:- Bulk |
| VP773-10001 | 功能描述:高速/模塊連接器 Viper 3U Daughter Card Kit Variant A RoHS:否 制造商:Molex 系列:iPass 產(chǎn)品類型: 排數(shù): 列數(shù): 位置/觸點數(shù)量:38 安裝角:Right 節(jié)距:0.8 mm 安裝風格:Plug 端接類型:SMD/SMT 外殼材料:Thermoplastic 觸點材料:High Performance Alloy (HPA) 觸點電鍍:Gold |
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