6
VP7615
12
Out
VSYNC
Vertical Sync - This signal goes active for 3 horizontal lines to mark the beginning of
each field. In Odd fields, it starts and ends when HSYNC and HACT are low. In Even
fields, it starts and ends when HSYNC and HACT are active. This signal’s polarity is
programmable, but defaults to active low on reset.
13
Out
HSYNC
Horizontal Sync - This signal goes active and returns inactive in the horizontal blanking
interval to mark the beginning of each line. This signal’s polarity is programmable, but
defaults to active low on reset.
28
Out
HACT
Horizontal Active - This signal is active when there is valid video data on the luminance
and chrominance busses. Data is valid only when this signal and VACT are active.
HACT can be programmed to only go active on active lines (HACT = HACT AND
VACT), but defaults at reset to active on all lines. This signal’s polarity is also program-
mable, but defaults to active high on reset.
29
Out
VACT
Vertical Active - This signal is active when there is valid video data on the luminance
and chrominance busses. Data is valid only when this signal and HACT are active.
VACT can be programmed to only go active on active lines during active pixels (VACT =
HACT AND VACT), but defaults at reset to active for entire lines only. This signal’s
polarity is also programmable, but defaults to active high on reset.
30
Out
FIELD
Field Flag - This signal indicates the field. When it is low, the field is odd. When it is
high, the field is even.
31
Out
BFLAG
Blue Flag - This signal indicates when Blue chrominance data is on the chrominance
bus.
35
In
CCSEL
CCIR 656 Select - When this input is high, the YY[7..0] bus carries multiplexed lumi-
nance and chrominance data in conformance with CCIR 656. When this signal is low,
the YY[7..0] bus carries only luminance data.
36
In
RCLK
Register Clock - This input clocks the control circuitry in the chip and must be running in
order to access the registers via the I
2
C bus. The frequency on this input should be
between 10 and 33 MHz.
38
In
INVI
Inverter In - This CMOS Schmidt trigger input controls the INVO output. This inverter
can be used to form an RC oscillator to drive the input RCLK. It is typically connected
through a resistor to INVO and through a capacitor to GND. This oscillator has a period
roughly equal to the time constant R*C.
37
Out
INVO
Inverter Out - This signal outputs the opposite level from that applied to INVI. If this
inverter is used to form an RC oscillator, this pin would be connected to RCLK.
42
In
OSXI
Oscillator Crystal Input - The crystal oscillator is another way to produce a clock for the
input RCLK. A crystal is connected between this input and OSXO.
41
Out
OSXO
Oscillator Crystal Output - A crystal is connected between this output and OSXI.
39
Out
OSCO
Oscillator Output - If the crystal oscillator is used to produce the register clock, this
CMOS output drives the RCLK input.
45
In
IAD3
I
2
C Address Select Bit 3 - The IAD[3..1] inputs select the I
2
C address that the chip will
respond to. The address is 0x60 + 8 * IAD3 + 4 * IAD2 + 2 * IAD1.
43
In
IAD2
I
2
C Address Select Bit 2
40
In
IAD1
I
2
C Address Select Bit 1
48
In
SDAI
Serial Data In - This input is connected to the I
2
C Data line. It may be connected
through a filter to reduce noise susceptibility.
47
Out
SDAO
Serial Data Out - This open-drain output connects directly to the I
2
C Data line.
46
Out
SDMN
Serial Data Monitor - This output is low when the SDAO output is driving low. This
output is high when the SDAO output is high impedance.
49
In
SCLI
Serial Clock In - This input is connected to the I
2
C Clock line. It may be connected
through a filter to reduce noise susceptibility.