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參數(shù)資料
| 型號(hào)： | VSC6048 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | High-Speed Octal Programmable Timing Generator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP160 |
| 封裝： | HEAT SINK, PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 2/18頁(yè) |
| 文件大?。?/td> | 204K |
| 代理商： | VSC6048 |
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VITESSE
Data Sheet
VSC6048
High-Speed Octal
Programmable Timing Generator
Page 2
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
8/28/00
G52335-0,Rev.4.0
Functional Description
Reference Clock Selection
Clock multiplication of x8 or x16 may be selected via the FSEL pin, requiring a reference clock of 100
±2.5MHz or 50 ±1.25MHz, respectively. For system applications with 800MHz on board clock, the CMU can
be bypassed by asserting BYP signal and RCK will accept an external 800MHz clock.
In Bypass mode (
BYP
= 1
, RCK
= 800MHz) the skew from INX to RCK at the pin is 550ps +/-250ps.
Table 1: Reference Clock Selection
X = don’t care.
Mode of Operations
There are 6 basic modes of operation. These modes are based on two inputs per channel (INA and INB) that
can be interleaved and refire rate. The maximum refire rate for full 10ns span is 100MHz, where the maximum
refire rate for 5ns span is 200MHz. The maximum refire rate at the input to the fine vernier must not be sooner
than 4 cycles of the high-speed clock (800MHz).
Table 2: Suggested Operating Modes
Data Input (INA, INB)
There are two interleaved inputs per channel. Each input is capable of running at full rate (200MHz). The
input is first retimed off of the internal 400MHz clock generated from the PLL. This means there is a 2.5ns edge
placement window that defines the setup time. This also means that the input pulse must span at least one
400MHz clock edge.
The inputs are low to high edge sensitive. Figure 1 illustrates an equivalent circuit of the input structure for
each channel. Note that the TSET input clock is generated based on the input data.
BYP
FSEL
RCK
0
0
1
0
100MHz
1
50MHz
X
800MHz
Program Rate
Interleaved
INA
INB
TSET[0:9] Range
200Mbps
100Mbps
200Mbps
100Mbps
200Mbps
100Mbps
Yes
Yes
No
No
No
No
100MHz
50MHz
200MHz
100MHz
Low
Low
100MHz
50MHz
Low
Low
200MHz
100MHz
000 to 1FF
000 to 3FF
000 to 1FF
000 to 3FF
000 to 1FF
000 to 3FF
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