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參數(shù)資料
| 型號(hào)： | VSC6048 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | High-Speed Octal Programmable Timing Generator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP160 |
| 封裝： | HEAT SINK, PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大?。?/td> | 204K |
| 代理商： | VSC6048 |
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VITESSE
Data Sheet
VSC6048
High-Speed Octal
Programmable Timing Generator
Page 4
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
8/28/00
G52335-0,Rev.4.0
Figure 3: Fine Vernier Calibration DAC Programming
DAC Calibration
Each fine vernier must be calibrated to a 1240ps span, one step (10ps) shorter than the 800MHz period
(1.25ns). This is accomplished by setting the fine vernier to maximum delay and adjusting the 6-bit calibration
DAC until the desired range has been achieved.
The calibration data is transferred into the device through a 3-bit serial interface. Refer to Figure 3 for the
programming sequence. Typical DCLK frequencies are 1MHz to 10MHz. Once the calibration value has been
transferred into the device, the data is written into the specified DAC by the rising edge of DCLK when
DAC_WR is HIGH. The address lines must remain stable from the enable of SHIFT to one cycle after the dis-
able of DAC_WR.
DAC Application
There are three DAC_REF pins on this device. Each pin supplies the reference for two or three calibration
DACs. In order to reduce crosstalk between verniers through the DAC_REF supply, it is recommended that
each DAC_REF pin be isolated from each other. This will reduce crosstalk between the the three channel
groups, however, it will not effect crosstalk between verniers within each group.
Table 3: DAC Reference Pin Identification
Outputs
Each channel has a differential ECL output. The output of the verniers is falling edge active. The shift reg-
ister propagates a 2ns pulse. The fine vernier then stretches the pulse width based on the programmed delay.
DAC_REF Pin #
1
18
40
Vernier Channels
0, 1, 2
3, 4
5, 6, 7
SHIFT
DCLK
DIN
DAC_WR
CAL_DAT
(internal)
ADR[2:0]
5
4
3
2
1
0
Vernier 0 DAC Data
X
X
X
X
X
5
4
3
2
1
0
X
X
X
X
1
2
3
4
5
6
1
2
3
4
5
6
Address for Vernier 0
Vernier 1 DAC Data
Address for Vernier 1
Shift Data Into
Calibration Register
Hold Data In
Calibration Register
One Test/Calibration Cycle
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