參數(shù)資料
型號: VSC7126
廠商: VITESSE SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: 1.0625 Gbits/sec Fibre Channel Transceiver
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP80
封裝: 14 X 14 MM, PLASTIC, QFP-80
文件頁數(shù): 13/16頁
文件大小: 223K
代理商: VSC7126
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 13
3/4/99
VITESSE
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
G52148-0, Rev. 4.3
65,63,59,57,
55,52,50,48,
45,43,64,62,
58,56,54,51,
49,47,44,42
R0:19
R
eceive Data Bus, Bits
0
thru
19
OUTPUTS - TTL
20-bit received character. Parallel data on this bus is clocked out on the rising edge of
RBC(0). R0 is the first bit received on RX+/RX-.
34
EWRAP
E
nable Internal
WRAP
Mode. INPUT - TTL
LOW for Normal Operation. When HIGH, an internal loopback path from the
transmitter to the receiver is enabled, TX+ = HIGH and TX- is LOW.
R
eceive Serial Inputs INPUTS - Differential PECL
The receiver inputs when EWRAP is LOW. Internally biased to VDD/2, with 3.3K
resistors to VDD and GND. (AC Coupling recommended)
R
ecovered
B
yte
C
lock and Complement OUTPUT - TTL
Recovered clock and complement derived from one twentieth of the RX+/- data stream.
The rising edge of RBC(0) corresponds to a new word on R0:19.
EN
able
C
omma
DET
ect. INPUT - TTL
Enables comma detection and word resynchronization when HIGH. When LOW, keeps
current word alignment and disables comma detection.
COM
ma
DET
ect OUTPUT - TTL
This output goes HIGH to indicate that R0:6 contains a Comma Character (‘0011111’).
COMDET will go HIGH only during a cycle when RBC(0) is falling. COMDET is
enabled by EN_CDET being HIGH.
T
ransmitter
EN
able INPUT - TTL
When LOW, the TX outputs transmit serial data. When HIGH, the TX+ is HIGH and the
TX- is LOW.
Link
UNUSE
OUTPUT - TTL
Normally is LOW. If R0:19 is all LOW or all HIGH and EWRAP is LOW, this output
will be asserted HIGH to indicate an open link on RX+/-.
70
69
RX+
RX-
39
38
RBC(0)
RBC(1)
27
EN_CDET
37
COMDET
35
TXEN#
66
LUNUSE
26
28
29
TEST1
TEST2
TEST3
VSS
VSST
VSSA
TEST Mode Pins INPUT - TTL
Factory test pins. Tie to VDD for normal operation.
1,21,30,68,72
40,41,60,61
74
7,13,25,32,33,
67,71,75
36,46,53
76,80
73
78
Digital Ground
Digital Ground for TTL Outputs
Analog Ground
VDD
Digital Power (3.3V)
VDDT
VDDP
VDDA
N/C
Digital Power for TTL outputs (3.3V)
Digital Power for PECL outputs (3.3V)
Analog Power (3.3V)
Not Internally Connected.
Pin #
Name
Description
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