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參數(shù)資料
| 型號： | VSC7126 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 1.0625 Gbits/sec Fibre Channel Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 223K |
| 代理商： | VSC7126 |
VITESSE
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
Page 6
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
3/4/99
G52148-0, Rev. 4.3
Figure 5: Receive Timing Waveforms
Table 2: Receive AC Characteristics
Parameters
Description
Min.
Max.
Units
Conditions
T
1
Data or COM_DET Valid
prior to RBC(0) fall
4
—
ns.
Measured between the 1.4V
point of RBC(0) and a valid
level of R0:19 or
COM_DET. All outputs
driving 10pF load.
Nominal delay is 20 bit
times.
Tested on sample basis
Between V
il(max)
and
V
ih(min)
, into 10 pf. load.
T
2
Data or COM_DET Valid
after RBC(0) fall
6.0
—
ns.
T
4
Deviation of RBC(0) falling
edge to falling edge delay
from nominal.
R0:19, COM_DET, RBC(0)
rise and fall time
Latency from RX to RBC(0)
falling and RO valid.
Skew between edges of
RBC(0) and RBC(1)
Data acquisition lock time @
1.0625Gb/s
-500
500
ps.
T
R
, T
F
0.7
2.4
ns.
R
lat
40 bc + 10 ns
59 bc + 10 ns
Bit
Clocks
bc = bit clock periods
T
SKEW
----
1.5
ns
T
LOCK
—
2.4
μ
s.
8B/10B IDLE pattern.
Tested on a sample basis
RBC(0)
R0:19 &
COM_DET
LUNUSE
T
2
Data Valid
Data Valid
T
1
T
3
Data Valid
RBC(1)
T
SKEW
NOTE: Probability of Recovery for data acquisition is 95% per section 5.3 of the FC-PH rev 4.3.
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