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參數(shù)資料
| 型號： | vt82c693 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | APOLLO PRO-PLUS |
| 中文描述： | 阿波羅專業(yè)普樂士 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 124K |
| 代理商： | VT82C693 |
VT82C693
Preliminary Revision 0.3
December 9, 1998
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2-
Features
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Full Featured Accelerated Graphics Port (AGP) Controller
Synchronous and pseudo-synchronous with the host CPU bus with optimal skew control
PCI
AGP
CPU
Mode
33 MHz
66 MHz
100 MHz
3x synchronous
33 MHz
66 MHz
66 MHz
2x synchronous
AGP v2.0 compliant
Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)
Supports 133MHz 2X mode for AD and SBA signaling
Pipelined split-transaction long-burst transfers up to 533 MB/sec
Eight level read request queue
Four level posted-write request queue
Thirty-two level (quadwords) read data FIFO (128 bytes)
Sixteen level (quadwords) write data FIFO (64 bytes)
Intelligent request reordering for maximum AGP bus utilization
Supports Flush/Fence commands
Graphics Address Relocation Table (GART)
One level TLB structure
Sixteen entry fully associative page table
LRU replacement scheme
Independent GART lookup control for host / AGP / PCI master accesses
Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver support
Concurrent PCI Bus Controller
PCI buses are synchronous / pseudo-synchronous to host CPU bus
33 MHz operation on the primary PCI bus
66 MHz PCI operation on the AGP bus
PCI-to-PCI bridge configuration on the 66MHz PCI bus
Supports up to five PCI masters
Peer concurrency
Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time
Zero wait state PCI master and slave burst transfer rate
PCI to system memory data streaming up to 132Mbyte/sec
PCI master snoop ahead and snoop filtering
Two lines of CPU to PCI posted write buffers
Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
Forty-eight levels (double-words) of post write buffers from PCI masters to DRAM
Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
Delay transaction from PCI master accessing DRAM
Read caching for PCI master reading DRAM
Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
Symmetric arbitration between Host/PCI bus for optimized system performance
Complete steerable PCI interrupts
PCI-2.1 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
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