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參數(shù)資料
| 型號： | vt82c693 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | APOLLO PRO-PLUS |
| 中文描述： | 阿波羅專業(yè)普樂士 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 124K |
| 代理商： | VT82C693 |
VT82C693
Preliminary Revision 0.3
December 9, 1998
-
4-
Overview
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O
VERVIEW
The
Apollo Pro-Plus
is a high performance, cost-effective and energy efficient chip set for the implementation of AGP / PCI / ISA
desktop and notebook personal computer systems from 66 MHz to 100 MHz based on 64-bit Socket 370 and Slot-1 (Intel
Pentium-II and Celeron) super-scalar processors.
PCKRUN#
PCI Bus
PCLK
MCLK
HCLK
Slot-1 or Socket 370
Host CPU
CKE#
Memory Bus
SMBus
Power Plane & Peripheral Control
GPIO and ACPI Events
ISA
VT82C693
Apollo Pro-Plus
North Bridge
492 BGA
SDRAM
EDO,
or FPG
3D
Graphics
Controller
AGP Bus
PCISTP#
BIOS ROM
GCKRUN#
IDE ATA/33
USB
VT82C596A
Mobile South
324 BGA
Keyboard / Mouse
CPUSTP#
Clock
Generator
HCLK
SMI# / STPCLK# / SLP#
GCLK
PCLK
SUSCLK,
SUSST1#
SMIACT#
Clock
Buffer
Figure 1. Apollo Pro-Plus System Block Diagram Using the VT82C596A Mobile South Bridge
The Apollo Pro-Plus chip set consists of the VT82C693 system controller (492 pin BGA) and the VT82C596A PCI to ISA bridge
(324 pin BGA). The system controller provides superior performance between the CPU, DRAM, AGP bus, and PCI bus with
pipelined, burst, and concurrent operation.
The VT82C693 supports eight banks of DRAMs up to 1GB. The DRAM controller supports standard Fast Page Mode (FPM)
DRAM, EDO-DRAM, and Synchronous DRAM (SDRAM), in a flexible mix / match manner. The Synchronous DRAM interface
allows zero wait state bursting between the DRAM and the data buffers at 100 MHz. The eight banks of DRAM can be composed
of an arbitrary mixture of 1M / 2M / 4M / 8M / 16MxN DRAMs. The DRAM controller also supports optional ECC (single-bit
error correction and multi-bit detection) or EC (error checking) capability separately selectable on a bank-by-bank basis. The
DRAM controller can run at either the host CPU bus frequency (66 /100 MHz) or at the AGP bus frequency (66 MHz) with built-in
PLL timing control.
The VT82C693 system controller also supports full AGP v2.0 capability for maximum bus utilization including 2x mode transfers,
SBA (SideBand Addressing), Flush/Fence commands, and pipelined grants. An eight level request queue plus a four level post-
write request queue with thirty-two and sixteen quadwords of read and write data FIFO's respectively are included for deep
pipelined and split AGP transactions. A single-level GART TLB with 16 full associative entries and flexible CPU / AGP / PCI
remapping control is also provided for operation under protected mode operating environments. Both Windows-95 VXD and
Windows-98 / NT5 miniport drivers are supported for interoperability with major AGP-based 3D and DVD-capable multimedia
accelerators.
The VT82C693 supports two 32-bit 3.3 / 5V system buses (one AGP and one PCI) that are synchronous / pseudo-synchronous to
the CPU bus. The chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five
levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation,
forty-eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are
supported such as snoop ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-back merged with PCI post
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