參數(shù)資料
型號: W25Q64CVSSIG
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 64M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝: 0.208 INCH, GREEN, SOIC-8
文件頁數(shù): 22/79頁
文件大小: 1086K
代理商: W25Q64CVSSIG
W25Q64CV
Publication Release Date: April 01, 2011
- 29 -
Revision C
7.2.12 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred from the W25Q64CV at
twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly
downloading code from Flash to RAM upon power-up or for applications that cache code-segments to
RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in Figure 11. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks is
“don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out
clock.
/CS
CLK
DI
(IO
0)
DO
(IO
1)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (3Bh)
High Impedance
8
9
10
28
29
30
32
33
34
35
36
37
38
39
6
4
2
0
24-Bit Address
23
22
21
3
2
1
0
*
31
/CS
CLK
DI
(IO
0)
DO
(IO
1)
Dummy Clocks
0
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
7
5
3
1
6
4
2
0
6
4
2
0
6
4
2
0
High Impedance
7
5
3
1
7
5
3
1
7
5
3
1
IO
0 switches from
Input to Output
6
7
Data Out 1
* Data Out 2
* Data Out 3
* Data Out 4
= MSB
*
Figure 11. Fast Read Dual Output Instruction Sequence Diagram
相關(guān)PDF資料
PDF描述
W25Q64CVZPAP 64M X 1 SPI BUS SERIAL EEPROM, PDSO8
WMS128K8C-25CQE 128K X 8 STANDARD SRAM, 25 ns, CDIP32
WMF512K8X-150DEC5 512K X 8 FLASH 5V PROM, 150 ns, CDSO32
WME128K8X-200DEC 128K X 8 EEPROM 5V, 200 ns, CDSO32
WMF512K8X-70FEM5 512K X 8 FLASH 5V PROM, 70 ns, CDFP32
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