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參數(shù)資料
| 型號： | W320-04HT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DRVR CPUOUT 200MHZ 56SSOP |
| 標準包裝： | 1,000 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:22 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
W320-04
.......................Document #: 38-07010 Rev. *C Page 5 of 16
Data Byte 1
Bit
Pin#
Name
Description
Type
Power On
Default
Bit 7
–
N/A
CPU Mult0 Value
R
N/A
Bit 6
52, 49, 45 CPU0:2
Three-State CPU0:2 during power down
0 = Normal; 1 = Three-stated
R/W
0
Bit 5
44, 45
CPU2
CPU2#
Allow Control of CPU2 with assertion of CPU_STOP#
0 = Not free running; 1 = Free running
R/W
0
Bit 4
48, 49
CPU1
CPU1#
Allow Control of CPU1 with assertion of CPU_STOP#
0 = Not free running;1 = Free running
R/W
0
Bit 3
51, 52
CPU0
CPU0#
Allow Control of CPU0 with assertion of CPU_STOP#
0= Not free running; 1 = Free running
R/W
0
Bit 2
44, 45
CPU2
CPU2#
CPU2 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 1
48, 49
CPU1
CPU1#
CPU1Output Enable
1 = Enabled; 0= Disabled
R/W
1
Bit 0
51, 52
CPU0
CPU0#
CPU0 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Data Byte 2
Bit
Pin#
Name
Pin Description
Type
Power On
Default
Bit 7
–
N/A
R
0
Bit 6
18
PCI6
PCI6 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 5
17
PCI5
PCI5 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 4
16
PCI4
PCI4 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 3
13
PCI3
PCI3 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 2
12
PCI2
PCI2 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 1
11
PCI1
PCI1 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 0
10
PCI0
PCI0 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Data Byte 3
Bit
Pin#
Name
Pin Description
Type
Power On
Default
Bit 7
38
DOT
DOT 48-MHz Output Enable
R/W
1
Bit 6
39
USB
USB 48-MHz Output Enable
R/W
1
Bit 5
7
PCI_F2
Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 4
6
PCI_F1
Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 3
5
PCI_F0
Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 2
7
PCI_F2
PCI_F2 Output Enable
R/W
1
Bit 1
6
PCI_F1
PCI_F1Output Enable
R/W
1
Bit 0
5
PCI_F0
PCI_F0 Output Enable
R/W
1
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