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參數(shù)資料
| 型號： | W320-04HT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DRVR CPUOUT 200MHZ 56SSOP |
| 標準包裝： | 1,000 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:22 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
W320-04
.......................Document #: 38-07010 Rev. *C Page 8 of 16
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Switching Characteristics[9] Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Max.
Unit
t1
All
Output Duty Cycle[10]
Measured at 1.5V
45
55
%
t3
USB, REF, DOT Falling Edge Rate
Between 2.4V and 0.4V
0.5
2.0
ns
t3
PCI,3V66
Falling Edge Rate
Between 2.4V and 0.4V
1.0
4.0
V/ns
t5
3V66[0:1]
3V66-3V66 Skew
Measured at 1.5V
500
ps
t5
66BUFF[0:2]
66BUFF-66BUFF Skew
Measured at 1.5V
175
ps
t6
PCI
PCI-PCI Skew
Measured at 1.5V
500
ps
t7
3V66, PCI
3V66-PCI Clock Jitter
3V66 leads. Measured at 1.5V
1.5
3.5
ns
t9
3V66
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
250
ps
t9
USB, DOT
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
350
ps
t9
PCI
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
500
ps
t9
REF
Cycle-Cycle Clock Jitter
Measured at 1.5V t9 = t9A – t9B
1000
ps
CPU 1.0V Switching Characteristics
t2
CPU
Rise Time
Measured differential waveform from
–0.35V to +0.35V
175
467
ps
t3
CPU
Fall Time
Measured differential waveform from
–0.35V to +0.35V
175
467
ps
t4
CPU
CPU-CPU Skew
Measured at Crossover
150
ps
t8
CPU
Cycle-Cycle Clock Jitter
Measured at Crossover t8 = t8A – t8B
150
ps
CPU
Rise/Fall Matching
Measured with test loads[11]
325
mV
Voh
CPU
High-level Output Voltage
including overshoot
Measured with test loads[11]
0.92
1.45
V
Vol
CPU
Low-level Output Voltage
including undershoot
Measured with test loads[11]
–0.2
0.35
V
Vcrossover
CPU
Crossover Voltage
Measured with test loads[11]
0.51
0.76
V
CPU 0.7V Switching Characteristics
t2
CPU
Rise Time
Measured single ended waveform from
0.175V to 0.525V
175
700
ps
t3
CPU
Fall Time
Measured single ended waveform from
0.175V to 0.525V
175
700
ps
t4
CPU
CPU-CPU Skew
Measured at Crossover
150
ps
t8
CPU
Cycle-Cycle Clock Jitter
Measured at Crossover t8 = t8A – t8B
With all outputs running
150
ps
CPU
Rise/Fall Matching
Measured with test loads[12, 13]
20
%
Voh
CPU
High-level Output Voltage
Including Overshoot
Measured with test loads[13]
0.85
V
Vol
CPU
Low-level Output Voltage
Including Undershoot
Measured with test loads[13]
–0.15
V
Vcrossover
CPU
Crossover Voltage
Measured with test loads[13]
0.28
0.43
V
Notes:
9. All parameters specified with loaded outputs.
10. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
11. The 1.0V test load is shown on the test circuit page.
12. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge.
13. The 0.7V test load is Rs = 33.2 ohm, Rp = 49.9 ohm in test circuit.
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