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參數(shù)資料
| 型號： | W332M72V-133SBI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 SYNCHRONOUS DRAM, 5.5 ns, PBGA208 |
| 封裝： | 16 X 22 MM, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 257K |
| 代理商： | W332M72V-133SBI |
1
White Electronic Designs
W332M72V-XBX
March 2006
Rev. 3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
GENERAL DESCRIPTION
The 256MByte (2Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally congured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 134,217,728-bit banks is organized as 8,192
rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 2Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging
one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-
speed, random-access operation.
The 2Gb SDRAM is designed to operate at 3.3V. An auto
refresh mode is provided, along with a power-saving,
power-down mode.
32Mx72 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
219 Plastic Ball Grid Array (PBGA), 32 x 25mm
3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 32M x 72
Weight: W332M72V-XBX – 3.5 grams typical
BENEFITS
40% SPACE SAVINGS
Reduced part count
Reduced I/O count
19% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Pinout compatible with lower desities
WEDPN4M72V-XB2X, WEDPN8M72V-XB2X and
WEDPN16M72V-XB2X
* This product is subject to change without notice.
Discrete Approach
ACTUAL SIZE
S
A
V
I
N
G
S
Area
5 x 265mm2 = 1328mm2
800mm2
40%
I/O
5 x 54 pins = 270 pins
219 Balls
19%
Count
25
32
11.9
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
White Electronic Designs
W332M72V-XBX
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W332M72V-133SBM | 制造商:Microsemi Corporation 功能描述:32M X 72 SDRAM, 3.3V, 133MHZ, 208 PBGA, MIL-TEMP. - Bulk |
| W332M72V-XBX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32Mx72 Synchronous DRAM |
| W332M72V-XSBX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32Mx72 Synchronous DRAM |
| W3330X6 | 制造商:n/a 功能描述:Ships in 2 days |
| W3331 | 功能描述:RF ANT TRACE 895MHZ 2.4GHZ SMD 制造商:pulselarsen antennas 系列:- 包裝:散裝 零件狀態(tài):在售 頻率組:UHF（300 MHz ~ 1 GHz），UHF（2 GHz ~ 3 GHz） 頻率（中心/帶）:895MHz，2.4GHz 頻率范圍:863MHz ~ 928MHz，2.4GHz ~ 2.5GHz 天線類型:PCB 印制線 頻帶數(shù):2 VSWR:- 回波損耗:-15dB 增益:3.5dBi 功率 - 最大值:3W 特性:- 端接:焊接 侵入防護:- 安裝類型:表面貼裝 高度（最大值）:0.031"（0.80mm） 應(yīng)用:藍牙，WLAN，Zigbee? 標準包裝:1 |
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