- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄245661 > W332M72V-133SBI (MICROSEMI CORP-PMG MICROELECTRONICS) 32M X 72 SYNCHRONOUS DRAM, 5.5 ns, PBGA208 PDF資料下載
參數(shù)資料
| 型號： | W332M72V-133SBI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 SYNCHRONOUS DRAM, 5.5 ns, PBGA208 |
| 封裝： | 16 X 22 MM, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大小： | 257K |
| 代理商： | W332M72V-133SBI |
6
White Electronic Designs
W332M72V-XBX
March 2006
Rev. 3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
FIGURE 4 – CAS LATENCY
OPERATING MODE
The normal operating mode is selected by setting M7and
M8 to zero; the other combinations of values for M7 and
M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and
WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
TABLE 2 – CAS LATENCY
SPEED
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
LATENCY = 2
CAS
LATENCY = 3
-100
≤ 75
≤ 100
-125
≤ 100
≤ 125
-133
≤ 100
≤ 133
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
CLK
Command
I/O
CLK
Command
I/O
T0
T1
T2
T3
T0
T1
T2
T3
T4
READ
NOP
CAS Latency = 2
DOUT
tLZ
tOH
tAC
READ
NOP
DOUT
tLZ
tOH
tAC
CAS Latency = 3
DON'T CARE
UNDEFINED
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the rst piece of output data. The latency can be set to
two or three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. The I/Os will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the
relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is programmed to two clocks, the I/Os will start driving
after T1 and the data will be valid by T2. Table 2 below
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WED3EG7233S265D3G | SYNCHRONOUS DRAM MODULE, DMA184 |
| W7NCF02GH11IS8CG | 128M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC |
| W7NCF02GH11IS5AG | 128M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC |
| W7NCF02GH11IS3DG | 128M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC |
| W25X80ALDAIZ | 1M X 8 FLASH 2.7V PROM, PDIP8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W332M72V-133SBM | 制造商:Microsemi Corporation 功能描述:32M X 72 SDRAM, 3.3V, 133MHZ, 208 PBGA, MIL-TEMP. - Bulk |
| W332M72V-XBX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32Mx72 Synchronous DRAM |
| W332M72V-XSBX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32Mx72 Synchronous DRAM |
| W3330X6 | 制造商:n/a 功能描述:Ships in 2 days |
| W3331 | 功能描述:RF ANT TRACE 895MHZ 2.4GHZ SMD 制造商:pulselarsen antennas 系列:- 包裝:散裝 零件狀態(tài):在售 頻率組:UHF（300 MHz ~ 1 GHz），UHF（2 GHz ~ 3 GHz） 頻率（中心/帶）:895MHz，2.4GHz 頻率范圍:863MHz ~ 928MHz，2.4GHz ~ 2.5GHz 天線類型:PCB 印制線 頻帶數(shù):2 VSWR:- 回波損耗:-15dB 增益:3.5dBi 功率 - 最大值:3W 特性:- 端接:焊接 侵入防護:- 安裝類型:表面貼裝 高度（最大值）:0.031"（0.80mm） 應(yīng)用:藍牙，WLAN，Zigbee? 標準包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。