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參數(shù)資料
| 型號(hào)： | W3E16M72S-200BI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁(yè)數(shù)： | 17/17頁(yè) |
| 文件大?。?/td> | 766K |
| 代理商： | W3E16M72S-200BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E16M72S-XBX
February 2005
Rev. 7
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
parameters. Input A10 determines whether one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. Otherwise BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command will
be treated as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
process of precharging.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above, but
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specic READ or WRITE command. A precharge of the
bank/row that is addressed with the READ or WRITE command
is automatically performed upon completion of the READ or
WRITE burst. AUTO PRECHARGE is nonpersistent in that it is
either enabled or disabled for each individual READ or WRITE
command. The device supports concurrent auto precharge if the
command to the other bank does not interrupt the data transfer
to the current bank.
AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. This “earliest valid
stage” is determined as if an explicit precharge command
was issued at the earliest possible time, without violating
tRAS (MIN).The user must not issue another command to
the same bank until the precharge time (tRP) is completed.
This is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating
tRAS (MIN).
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. Each DDR SDRAM
requires AUTO REFRESH cycles at an average interval
of 7.8125μs (maximum).
To allow for improved efciency in scheduling and switching
between tasks, some exibility in the absolute refresh
interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM,
meaning that the maximum absolute interval between any
AUTO REFRESH command and the next AUTO REFRESH
command is 9 x 7.8125μs (70.3μs). This maximum absolute
interval is to allow future support for DLL updates internal
to the DDR SDRAM to be restricted to AUTO REFRESH
cycles, without allowing excessive drift in tAC between
updates.
Although not a JEDEC requirement, to provide for future
functionality features, CKE must be active (High) during
the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered
and ends tRFC later.
SELF REFRESH*
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR
SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is
automatically disabled upon entering SELF REFRESH and
is automatically enabled upon exiting SELF REFRESH (200
clock cycles must then occur before a READ command
can be issued). Input signals except CKE are “Don’t Care”
during SELF REFRESH.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable prior to CKE go-
ing back HIGH. Once CKE is HIGH, the DDR SDRAM
must have NOP commands issued for tXSNR, because
time is required for the completion of any internal refresh
in progress.
A simple algorithm for meeting both refresh and DLL re-
quirements is to apply NOPs for 200 clock cycles before
applying any other command.
* Self refresh available in commercial and industrial temperatures only.
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| W3E16M72SR-200BM | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| W3E16M72SR-200BC | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| W3E16M72SR-200BM | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E16M72S-200BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx72 DDR SDRAM |
| W3E16M72S-250BC | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E16M72S-250BI | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E16M72S-250BM | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 250 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E16M72S-266BC | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 266 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
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