- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄203626 > W3E16M72S-266BI (WHITE ELECTRONIC DESIGNS CORP) 16M X 72 DDR DRAM, 0.75 ns, PBGA219 PDF資料下載
參數(shù)資料
| 型號(hào)： | W3E16M72S-266BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 766K |
| 代理商： | W3E16M72S-266BI |
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E16M72S-XBX
February 2005
Rev. 7
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register denition, command
descriptions and device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predened manner. Operational procedures other than
those specied may result in undened operation. Power
must rst be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the system VTT). VTT must be applied
after VCCQ to avoid device latch-up, which may cause
permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident
with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after VCC is applied.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven in
normal operation (by a read access). After all power supply
and reference voltages are stable, and the clock is stable,
the DDR SDRAM requires a 200μs delay prior to applying
an executable command.
Once the 200μs delay has been satised, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satised.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required. Following
these requirements, the DDR SDRAM is ready for normal
operation.
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs
and by the memory contoller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
The 128MB DDR SDRAM operates from a differential clock
(CLK and CLK#); the crossing of CLK going HIGH and CLK#
going LOW will be referred to as the positive edge of CLK.
Commands (address and control signals) are registered
at every positive edge of CLK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the burst
access.
The pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high
effective bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3E16M72S-200BI | 16M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| W3E16M72SR-200BM | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| W3E16M72SR-200BC | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| W3E16M72SR-200BM | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| W3EG2128M72AFSR262AD3M | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E16M72S-266BM | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 266 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E16M72S-333BC | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 333 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E16M72S-333BI | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 333 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E16M72S-333BM | 制造商:Microsemi Corporation 功能描述:16M X 72 DDR, 2.5V, 333 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E16M72SR-200BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。