- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄203626 > W3E16M72SR-200BM (WHITE ELECTRONIC DESIGNS CORP) 16M X 72 DDR DRAM, 0.75 ns, PBGA219 PDF資料下載
參數(shù)資料
| 型號(hào)： | W3E16M72SR-200BM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁(yè)數(shù)： | 15/16頁(yè) |
| 文件大?。?/td> | 671K |
| 代理商： | W3E16M72SR-200BM |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E16M72SR-XBX
February 2005
Rev. 2
NOTES:
1.
CKE is HIGH for all commands shown except SELF REFRESH.
2.
A0-12 dene the op-code to be written to the selected Mode Register. BA0, BA1
select either the mode register (0, 0) or the extended mode register (1, 0).
3.
A0-12 provide row address, and BA0, BA1 provide bank address.
4.
A0-8 provide column address; A10 HIGH enables the auto precharge feature (non
persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.
5.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
6.
This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
8.
Applies only to read bursts with auto precharge disabled; this command is
undened (and should not be used) for READ bursts with auto precharge enabled
and for WRITE bursts.
9.
DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-12 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 selects
the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open
for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-8
selects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the D/Qs
is written to the memory array subject to the DQM input
logic level appearing coincident with the data. If a given
DQM signal is registered LOW, the corresponding data
REGISTER FUNCTION TABLE
INPUTS
OUTPUT
Q
RESET#
RCK
RCK#
INPUT
HH
H
LL
H
L or H
X
Q0
L
X, or oating
L
TRUTH TABLE – COMMANDS (NOTE 1)
NAME (FUNCTION)
CS#
RAS#
CAS#
WE#
ADDR
DESELECT (NOP) (9)
H
X
NO OPERATION (NOP) (9)
L
H
X
ACTIVE (Select bank and activate row) (3)
L
H
Bank/Row
READ (Select bank and column, and start READ burst) (4)
L
H
L
H
Bank/Col
WRITE (Select bank and column, and start WRITE burst) (4)
L
H
L
Bank/Col
BURST TERMINATE (8)
L
H
L
X
PRECHARGE (Deactivate row in bank or banks) ( 5)
L
H
L
Code
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
L
H
X
LOAD MODE REGISTER (2)
L
Op-Code
TRUTH TABLE – DM OPERATION
NAME (FUNCTION)
DM
DQs
WRITE ENABLE (10)
L
Valid
WRITE INHIBIT (10)
H
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3EG2128M72AFSR262AD3M | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W3EG2128M72AFSR335AD3S | 256M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| W3EG264M72EFSU265D4SG | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| W3EG64128S335AD4 | 128M X 64 DDR DRAM MODULE, DMA200 |
| W3EG64128S335AD4 | 128M X 64 DDR DRAM MODULE, DMA200 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E16M72SR-225BC | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
| W3E16M72SR-225BI | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
| W3E16M72SR-225BM | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
| W3E16M72SR-266BC | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
| W3E16M72SR-266BI | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。