- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄203626 > W3E16M72SR-200BM (WHITE ELECTRONIC DESIGNS CORP) 16M X 72 DDR DRAM, 0.75 ns, PBGA219 PDF資料下載
參數(shù)資料
| 型號： | W3E16M72SR-200BM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 671K |
| 代理商： | W3E16M72SR-200BM |
13
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E16M72SR-XBX
February 2005
Rev. 2
NOTES:
1.
All voltages referenced to VSS.
2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related specications
and device operation are guaranteed for the full voltage range specied.
3.
Outputs measured with equivalent load:
50Ω
Reference
Point
30pF
Output
(VOUT)
VTT
4.
AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specications are guaranteed for the specied AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
5.
The AC and DC input level specications are as dened in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6.
VREF is expected to equal VCCQ/2 of the transmitting device and to track variations
in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may
not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV
for DC error and an additional ±25mV for AC noise. This measurement is to be
taken at the nearest VREF by-pass capacitor.
7.
VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track variations
in the DC level of VREF.
8.
VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
9.
The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device
and must track variations in the DC level of the same.
10. ICC is dependent on output loading and cycle rates. Specied values are obtained
with minimum cycle time with the outputs open.
11. Enables on-chip refresh and address counters.
12. ICC specications are tested after the device is properly initialized, and is averaged
at the dened cycle rate.
13. This parameter is not tested but guaranteed by design. tA = 25°C, F = 1 MHz
14. Command/Address input slew rate = 0.5V/ns. For 266 MHz with slew rates 1V/ns
and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns,
timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in
slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the
slew rate exceeds 4.5V/ns, functionality is uncertain.
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which
CK and CK# cross; the input reference level for signals other than CK/CK# is VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period
before VREF stabilizes, CKE 0.3 x VCCQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point
indicated in Note 3, is VTT.
18. tHZ and tLZ transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specic voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
19. The maximum limit for this parameter is not a device limit. The device will operate
with a greater value for this parameter, but system performance (bus turnaround)
will degrade accordingly.
20. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on tDQSS.
22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets
the minimum absolute value for the respective parameter. tRAS (MAX) for ICC
measurements is the largest multiple of tCK that meets the maximum absolute value
for tRAS.
23. The refresh period 64ms. This equates to an average refresh rate of 7.8125μs.
However, an AUTO REFRESH command must be asserted at least once every
70.3μs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
25. The valid data window is derived by achieving other specications - tHP (tCK/2), tDQSQ, and
tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty
cycle and a practical data valid window can be derived. The clock is allowed a maximum
duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio.
The data valid window derating curves are provided below for duty cycles ranging between
50/50 and 45/55.
26. Referenced to each output group: DQS0 with DQ0-DQ7; and DQS1 with DQ8-DQ15 of each
chip.
27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby).
28. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
160
140
120
100
80
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
IOUT
(mA)
Maximum
Nominal high
Nominal low
Minimum
FIGURE A – PULL-DOWN CHARACTERISTICS
FIGURE B – PULL-UP CHARACTERISTICS
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
0.0
0.5
1.0
1.5
2.0
2.5
VCCQ - VOUT (V)
IOUT
(mA)
Maximum
Nominal high
Nominal low
Minimum
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3EG2128M72AFSR262AD3M | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W3EG2128M72AFSR335AD3S | 256M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| W3EG264M72EFSU265D4SG | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| W3EG64128S335AD4 | 128M X 64 DDR DRAM MODULE, DMA200 |
| W3EG64128S335AD4 | 128M X 64 DDR DRAM MODULE, DMA200 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E16M72SR-225BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
| W3E16M72SR-225BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
| W3E16M72SR-225BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
| W3E16M72SR-266BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
| W3E16M72SR-266BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx72 Registered DDR SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。