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參數(shù)資料
| 型號： | W3EG2256M72ASSR262JD3MG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 512M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | ROHS COMPLIANT, DIMM-184 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 217K |
| 代理商： | W3EG2256M72ASSR262JD3MG |
W3EG2256M72ASSR-JD3
-AJD3
5
White Electronic Designs
November, 04
Rev. 3
PRELIMINARY
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C
≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
Parameter
Symbol
Rank 1
Conditions
DDR266:@CL=2, 2.5
Max
DDR200@CL=2
Max
Units
Rank 2
Standby
State
Operating Current
IDD0
One device bank; Active - Precharge; tRC = tRC
(MIN); tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and
control inputs changing once every two cycles.
4680
4230
mA
IDD3N
Operating Current
IDD1
One device bank; Active-Read-Precharge Burst
= 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA;
Address and control inputs changing once per
clock cycle.
5310
4860
mA
IDD3N
Precharge Power-
Down Standby Current
IDD2P
All device banks idle; Power-down mode; tCK =
tCK (MIN); CKE = (low)
360
rnA
IDD2P
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address and other
control inputs changing once per clock cycle. VIN
= VREF for DQ, DQS and DM.
2340
2160
mA
IDD2F
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down mode; tCK
(MIN); CKE = (low)
1260
1080
mA
IDD3P
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank;
Active-Precharge;tRC = tRAS (MAX); tCK = tCK
(MIN); DQ, DM and DQS inputs changing twice
per clock cycle; Address and other control inputs
changing once per clock cycle.
1800
1620
mA
IDD3N
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); lOUT = 0mA.
5760
5220
mA
IDD3N
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle.
5940
5400
rnA
IDD3N
Auto Refresh Current
IDD5
tRC = tRC (MIN)
7920
7560
mA
IDD3N
Self Refresh Current
IDD6
CKE
≤ 0.2V
324
mA
IDD6
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only during
Active Read or Write commands.
11250
10350
mA
IDD3N
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG2256M72ASSR262JD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4GB - 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG2256M72ASSR263AJD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4GB - 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG2256M72ASSR263JD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4GB - 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG2256M72ASSR265AJD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4GB - 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG2256M72ASSR265JD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4GB - 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
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