- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄203626 > W3EG264M72EFSU265D4SG (WHITE ELECTRONIC DESIGNS CORP) 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 PDF資料下載
參數(shù)資料
| 型號： | W3EG264M72EFSU265D4SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SO-DIMM-200 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 210K |
| 代理商： | W3EG264M72EFSU265D4SG |
W3EG264M72EFSUxxxD4
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
September 2004
Rev. 0
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
0°C < TA <+70°C; VCC = VCCQ = +2.5V ±0.2V
AC CHARACTERISTICS
403
335
262
265
UNITS NOTES
RAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Address and control input setup time (slow slew rate)
tISS
0.8
1
ns
12
Address and Control input pulse width (for each
input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
12
15
ns
DQ-DQS hold, DQS to rst DQ to go non-valid, per
access
tQH
tHP - tQHS
ns
22, 23
Data hold skew factor
tQHS
0.50
0.75
ns
ACTIVE to PRECHARGE command
tRAS
40
70,000
42
70,000
40
120,000
40
120,000
ns
30, 47
ACTIVE to READ with Auto precharge command
tRAP
15
18
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command
period
tRC
55
60
65
ns
AUTO REFRESH command period
tRFC
70
72
75
78
ns
42
ACTIVE to READ or WRITE delay
tRCD
15
18
15
20
ns
PRECHARGE command period
tRP
15
18
15
20
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
37
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
37
ACTIVE bank a to ACTIVE bank b command
tRRD
10
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0000
ns
18, 19
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
17
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
1111
tCK
Data valid output window
NA
tQH -tDQSQ
tQH - tDQSQ
ns
22
REFRESH to REFRESH command interval
tREFC
70.3
μs21
Average periodic refresh interval
tREFI
7.8
μs21
Terminating voltage delay to VDD
tVTD
0000
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
相關PDF資料 |
PDF描述 |
|---|---|
| W3EG64128S335AD4 | 128M X 64 DDR DRAM MODULE, DMA200 |
| W3EG64128S335AD4 | 128M X 64 DDR DRAM MODULE, DMA200 |
| W3EG64128S202BD4 | 128M X 64 DDR DRAM MODULE, DMA200 |
| W3EG64128S265AD4 | 128M X 64 DDR DRAM MODULE, DMA200 |
| W3EG6462S335D3 | 64M X 64 DDR DRAM MODULE, 0.7 ns, DMA184 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG264M72EFSU335D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA |
| W3EG264M72EFSU403D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA |
| W3EG264M72EFSUXXXD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA |
| W3EG64128S202AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG64128S202BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
發(fā)布緊急采購，3分鐘左右您將得到回復。