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參數(shù)資料
| 型號(hào)： | W3EG6432S202JD3 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | ROHS COMPLIANT, DIMM-184 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 405K |
| 代理商： | W3EG6432S202JD3 |
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White Electronic Designs
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
December 2006
Rev. 7
PRELIMINARY
W3EG6432S-D3
-JD3
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C TA 70°C, VCC = VCCQ = 2.5V ± 0.2V, VCC = VCCQ = 2.6V ± 0.1V (200MHz)V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
DDR400@
CL=3
Max
DDR333@
CL=2.5-3-3
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
DDR200@
CL=2
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
1080
1000
mA
Operating Current
IDD1
One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
1360
1200
mA
Precharge Power-
Down Standby
Current
IDD2P
All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
32
rnA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ,
DQS and DM.
480
400
360
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down
mode; tCK (MIN); CKE=(low)
320
240
200
mA
Active Standby
Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
560
480
400
mA
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; TCK= TCK (MIN); lOUT = 0mA.
1600
1400
1200
mA
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK=tCK (MIN); DQ,DM and DQS
inputs changing once per clock cycle.
1560
1400
1200
rnA
Auto Refresh Current
IDD5
tRC = tRC (MIN)
2080
2040
1880
mA
Self Refresh Current
IDD6
CKE 0.2V
32
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK (MIN); Address and control
inputs change only during Active Read
or Write commands.
3760
3280
2800
mA
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