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參數(shù)資料
| 型號： | W3H128M72ER-667SBC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM, 0.5 ns, PBGA255 |
| 封裝： | 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255 |
| 文件頁數(shù)： | 6/34頁 |
| 文件大?。?/td> | 1028K |
| 代理商： | W3H128M72ER-667SBC |
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W3H128M72ER-XNBX
14
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2009
Rev. 6
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
EXTENDED MODE REGISTER 2
The extended mode register 2 (EMR2) controls functions
beyond those controlled by the mode register. Currently
all bits in EMR2 are reserved, as shown in Figure 8. The
EMR2 is programmed via the LM command and will
retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is
performed correctly.
Bit E7 (A7) must be programmed as"1" to provide a faster
refresh rate on devices if the TCASE exceeds 85°C
EMR2 must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specified time tMRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecied operation.
EXTENDED MODE REGISTER 3
The extended mode register 3 (EMR3) controls functions
beyond those controlled by the mode register. Currently,
all bits in EMR3 are reserved, as shown in Figure 9.
The EMR3 is programmed via the LM command and will
retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is
performed correctly.
EMR3 must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specified time tMRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecied operation.
COMMAND TRUTH TABLES
The following tables provide a quick reference of DDR2
SDRAM available commands, including CKE power-down
modes, and bank-to-bank commands.
FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
0
1
0
1
Mode Register Definition
M16
M17
0
0
1
M15
0
0
Mode register (MR)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
A9
A7 A6 A5 A4 A3
A8
A2
A1 A0
Extended Mode
Register (Ex)
Address Bus
97
6
5
4
3
82
1
0
A10
A12
A11
BA0
BA1
10
11
12
13
00
0
14
15
A13
A14
EMR3
BA2
16
17
Note: 1. E14 (A14)-E0 (A0) are reserved for future use and must be programmed to
"0." A14 is not used in this device.
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| W3H128M72ER2-400SBI | 128M X 72 DDR DRAM, 0.6 ns, PBGA255 |
| W3H32M64E-400SBM | 32M X 64 DDR DRAM, 0.6 ns, PBGA208 |
| W3H32M64E-667SBC | 32M X 64 DDR DRAM, 0.65 ns, PBGA208 |
| W3H32M64EA-400SBC | 32M X 64 DDR DRAM, PBGA208 |
| W3H32M64EA-667SBM | 32M X 64 DDR DRAM, PBGA208 |
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