參數(shù)資料
型號(hào)： W3H64M72E-533ESM
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： DRAM
英文描述： 64M X 72 DDR DRAM, 0.5 ns, PBGA208
封裝： 17 X 23 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁(yè)數(shù)： 17/30頁(yè)
文件大?。?/td> 999K
代理商： W3H64M72E-533ESM
W3H64M72E-XSBX
24
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2006
Rev. 2
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specications without notice.
DDR2 ICC SPECIFICATIONS AND CONDITIONS
VCC = 1.8V ±0.1V; -55°C ≤ TA ≤ 125°C
Symbol
Proposed Conditions
533 CL4
400 CL3
Units
ICC0
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
675
550
mA
ICC1
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDAD6W
650
600
mA
ICC2P
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
35
mA
ICC2Q
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
325
225
mA
ICC2N
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
350
250
mA
ICC3P
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
200
150
mA
Slow PDN Exit MRS(12) = 1
50
mA
ICC3N
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
375
300
mA
ICC4W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP
= tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
1,000
900
mA
ICC4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDAD6W
1,300
1,250
mA
ICC5
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,350
1,250
mA
ICC6
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
35
mA
ICC7
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC =
tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for
detailed timing conditions
1,750
1,650
mA
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W3H64M72E-667ES 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
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