參數(shù)資料
型號(hào)： W3H64M72E-533ESM
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： DRAM
英文描述： 64M X 72 DDR DRAM, 0.5 ns, PBGA208
封裝： 17 X 23 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁數(shù)： 4/30頁
文件大?。?/td> 999K
代理商： W3H64M72E-533ESM
W3H64M72E-XSBX
12
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2006
Rev. 2
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specications without notice.
EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
on die termination (ODT) (RTT), posted AL, off-chip driver
impedance calibration (OCD), DQS# enable/disable,
RDQS/RDQS# enable/disable, and output disable/enable.
These functions are controlled via the bits shown in
Figure 7. The EMR is programmed via the LOAD MODE
(LM) command and will retain the stored information
until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the
memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait
the specied time tMRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecied operation.
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
DLL
Posted CAS#
out
A9
A7 A6 A5 A4 A3
A8
A2
A1 A0
Extended Mode
Register (Ex)
Address Bus
97
6
5
4
3
82
1
0
A10
A12
A11
BA0
BA1
10
11
12
13
02
14
Poste d CA S# A dditive Laten cy (AL)
0
1
2
3
4
Reserved
E3
0
1
0
1
0
1
0
1
E4
0
1
0
1
E5
0
1
0
1
DLL Ena ble
Enable (Normal)
Disable (Test/Debug)
E0
15
0
1
RDQ S Ena ble
No
Yes
E11
OCD Program
A13
ODS
RTT
DQS#
0
1
DQ S# Ena ble
Enable
Disable
E10
RDQS
Rtt (nominal)
RTT disabled
75
150
50
E2
0
1
0
1
E6
0
1
0
1
Outputs
Enabled
Disabled
E12
0
1
0
1
Mo de Regi ster Set
Mode register set (MRS)
Extended mode register (EMRS)
Extended mode register (EMRS2)
Extended mode register (EMRS3)
E15
0
0
1
E14
MRS
OCD Operation
OCD not supported 1
Reserved
OCD default state
1
E7
0
1
0
1
E8
0
1
0
1
E9
0
1
0
1
Output Drive Strength
E1
Full strength (18
target)
Reduced strength (40
target)
RTT
E16
0
0
BA2
16
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,
then must be set to "0" before initialization is nished, as detailed in the
initialization procedure.
2.. E13 (A13) is not used on this device.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W3H64M72E-533SB 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H64M72E-533SBC 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk
W3H64M72E-533SBI 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY
W3H64M72E-533SBM 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA MIL-TEMP. - Bulk
W3H64M72E-667ES 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
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