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參數(shù)資料
| 型號(hào)： | W3H64M72E-667SBCF |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM, PBGA208 |
| 封裝： | 16 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-208 |
| 文件頁(yè)數(shù)： | 19/32頁(yè) |
| 文件大?。?/td> | 944K |
| 代理商： | W3H64M72E-667SBCF |
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W3H64M72E-XSBX
W3H64M72E-XSBXF
26
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
December 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 9
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC TIMING PARAMETERS
(continued)
-55°C ≤ TA < +125°C
Parameter
Symbol
667Mbs CL6
533Mbs CL5
400Mbs CL4
Unit
Min
Max
Min
Max
Min
Max
Data
DQ hold skew factor
t
QHS
-
340
-
400
-
450
ps
DQ output access time from CK/
CK#
t
AC
-450
450
-500
+500
-600
+600
ps
Data-out high impedance window
from CK/CK#
t
HZ
tAC(MAX)
ps
DQS Low-Z window from CK/CK#
t
LZ1
tAC(MN)
tAC(MAX)
tAC(MN)
tAC(MAX)
tAC(MN)
tAC(MAX)
ps
DQ Low-Z window from CK/CK#
t
LZ2
2*tAC(MN)
tAC(MAX)
2*tAC(MN)
tAC(MAX)
2*tAC(MN)
tAC(MAX)
ps
DQ and DM input setup time
relative to DQS
t
DSa
300
350
400
ps
t
DHa
300
350
400
ps
t
DSb
100
150
ps
t
DHb
175
225
275
ps
DQ and DM input pulse width (for
each input)
t
DIPW
0.35
ps
Data hold skew factor
t
QHS
340
400
450
ps
DQ-DQS hold, DQS to rst DQ to
go nonvalid, per access
t
QH
tHP - tQHS
ps
Data valid output window (DVW)
t
DVW
tQH - tDQSQ
ns
Data
Strobe
DQS input high pulse width
t
DQSH
0.35*tCK
tCK
DQS input low pulse width
t
DQSL
0.35*tCK
tCK
DQS output access time fromCK/
CK#
t
DQSCK
-400
400
-450
+450
-500
+500
ps
DQS falling edge to CK rising -
setup time
t
DSS
0.2*tCK
tCK
DQS falling edge from CK rising -
hold time
t
DSH
0.2*tCK
tCK
DQS-DQ skew, DOS to last DQ
valid, per group, per access
t
DQSQ
240
300
350
ps
DQS read preamble
t
RPRE
0.9*tCK
1.1*tCK
0.9*tCK
1.1*tCK
0.9*tCK
1.1*tCK
tCK
DQS read postamble
t
RPST
0.4*tCK
0.6*tCK
0.4*tCK
0.6*tCK
0.4*tCK
0.6*tCK
tCK
DQS write preamble setup time
t
WPRES
0
ps
DQS write preamble
t
WPRE
0.35
0.25
tCK
DQS write postamble
t
WPST
0.4*tCK
0.6*tCK
0.4*tCK
0.6*tCK
0.4*tCK
0.6*tCK
tCK
Positive DQS latching edge to
associated clock edge
t
DQSS
-0.25*tCK
0.25*tCK
-0.25*tCK
0.25*tCK
-0.25*tCK
0.25*tCK
tCK
Write command to rst DQS
latching transition
WL-TDQSS
WL+TDQSS
WL-TDQSS
WL+TDQSS
WL-TDQSS
WL+TDQSS
tCK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H64M72E-667SBI | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 667MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk |
| W3H64M72E-667SBM | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 667MHZ, 208PBGA MIL-TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H64M72EERXXXAD7MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3H64M72EERXXXAD7SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3H64M72E-ES | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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