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參數(shù)資料
| 型號： | W3HG128M64EEU665D4ISG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 64 DDR DRAM MODULE, 0.45 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 221K |
| 代理商： | W3HG128M64EEU665D4ISG |
W3HG128M64EEU-D4
November 2006
Rev. 2
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION
VCC = +1.8V ±0.1V
Clock
AC Characteristics
Symbol
806
665
534
403
Units
Notes
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Clock cycle time
CL = 6
t
CK (6)
3,000 8,000
------
ps
CL = 5
t
CK (5)
3,000 8,000 3,000 8,000
----
ps
16, 22,
36, 38
CL = 4
t
CK (4)
3,000 8,000 3,750 8,000 3,750 8,000 5,000 8,000
ps
CL = 3
t
CK (3)
-
5,000 8,000 5,000 8,000 5,000 8,000
ps
CK high-level width
t
CHAVG
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
45
CK low-level width
t
CLAVG
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
Half clock period
t
HP
MIN
(
tCH,tCL)
MIN
(
tCH,tCL)
MIN
(
tCH,tCL)
MIN
(
tCH,tCL)
ps
46
Clock
(Absolute)
Absolute tCk
t
CKabs
tCKAVG+
(MIN)+
tJITPER
(MIN)
tCKAVG+
(MAX)+
tJITPER
(MAX)
tCKAVG+
(MIN)+
tJITPER
(MIN)
tCKAVG+
(MAX)+
tJITPER
(MAX)
tCKAVG+
(MIN)+
tJITPER
(MIN)
tCKAVG+
(MAX)+
tJITPER
(MAX)
tCKAVG+
(MIN)+
tJITPER
(MIN)
tCKAVG+
(MAX)+
tJITPER
(MAX)
ps
Absolute CK high-level width
t
CHabs
tCKAVG
(MIN)*tCH
AVG+tJIT
DTY(MIN)
tCKAVG
(MAX)*tCH
AVG+tJIT
DTY(MAX)
tCKAVG
(MIN)*tCH
AVG+tJIT
DTY(MIN)
tCKAVG
(MAX)*tCH
AVG+tJIT
DTY(MAX)
tCKAVG
(MIN)*tCH
AVG+tJIT
DTY(MIN)
tCKAVG
(MAX)*tCH
AVG+tJIT
DTY(MAX)
tCKAVG
(MIN)*tCH
AVG+tJIT
DTY(MIN)
tCKAVG
(MAX)*tCH
AVG+tJIT
DTY(MAX)
ps
Absolute CK low-level width
t
CLabs
tCKAVG
(MIN)*
tCLAVG
(MIN)+tJIT
DTY(MIN)
tCKAVG
(MAX)*
tCLAVG
(MAX)+
tJIT
DTY(MIN)
tCKAVG
(MIN)*
tCLAVG
(MIN)+tJIT
DTY(MIN)
tCKAVG
(MAX)*
tCLAVG
(MAX)+
tJIT
DTY(MIN)
tCKAVG
(MIN)*
tCLAVG
(MIN)+tJIT
DTY(MIN)
tCKAVG
(MAX)*
tCLAVG
(MAX)+
tJIT
DTY(MIN)
tCKAVG
(MIN)*
tCLAVG
(MIN)+tJIT
DTY(MIN)
tCKAVG
(MAX)*
tCLAVG
(MAX)+
tJIT
DTY(MIN)
ps
Clock
jitter
Clock jitter - period
t
JITPER
-125
125
-125
125
-125
125
-125
125
ps
39
Clock jitter - half period
t
JITDUTY
-125
125
-125
125
-125
125
-150
150
ps
40
Clock jitter - cycle to cycle
t
JITCC
250
ps
41
Cumulative jitter error, 2 cycles
t
ERR2per
-175
175
-175
175
-175
175
-175
175
ps
42
Cumulative jitter error, 3 cycles
t
ERR3per
-225
225
-225
225
-225
225
-225
225
ps
42
t
ERR4per
-250
250
-250
250
-250
250
-250
250
ps
42
Cumulative jitter error, 5cycles
t
ERR5per
-250
250
-250
250
-250
250
-250
250
ps
42, 48
Cumulative jitter error, 6-10 cycles
t
ERR6-10per -350
350
-350
350
-350
350
-350
350
ps
42, 48
Cumulative jitter error, 11-50 cycles
t
ERR11-50per -450
450
-450
450
-450
450
-450
450
ps
42
Note:
AC specication is based on
MICRON components. Other DRAM manufactures specication may be different.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3HG128M64EEU665D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEU806D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEU-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEUXXXD4IMG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEUXXXD4ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
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