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參數(shù)資料
| 型號： | W3HG2256M72ACER534AD6MG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 512M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大小： | 296K |
| 代理商： | W3HG2256M72ACER534AD6MG |
W3HG2256M72ACER-AD6
ADVANCED
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
June 2007
Rev. 1
Notes
1.
All voltages referenced to VSS
2.
Tests for AC timing, ICC, and electrical AC and DC characteristics
may be conducted at nominal reference/supply voltage levels, but
the related specications and device operation are guaranteed for
the full voltage range specied.
3.
Outputs measured with equivalent load:
4.
AC timing and ICC tests may use a VIL to VIH swing of up to 1.0V
in the test environment parameter specications are guaranteed
for the specied AC input levels under normal use conditions. The
minimum slew rate for the input signals used to test the device is
1.0V/ns for signals in the range between VIL (AC) and VIH (AC).
Slew derates less than 1.0V/ns require the timing parameters to be
rated as specied.
5.
The AC and DC input level specications are as dened in the
SSTL_18 standard (i.e., the receiver will effectively switch as a
result of the signal crossing the AC input level and will remain in
that state as long as the signal does not ring back above [below]
the DC input LOW [HIGH] level).
6.
1. There are two sets of values listed for command/address: tISa,
tIHa and tISb, tIHb. The tISa, tIHa values (for reference only) are
equivalent to the baseline values of tISb, tIHb at VREF when
the slew rate is 1 V/ns. The baseline values, tISb, tIHb, are the
JEDEC-dened values, referenced from the logic trip points. tISb
is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling
signal, while tIHb is referenced from VIL(DC) for a rising signal and
VIH(DC) for a falling signal. If the command/address slew rate is
not equal to 1 V/ns, then the baseline values must be derated by
adding the values.
7.
1. The values listed are for the differential DQS strobe (DQS and
DQS#) with a differential slew rate of 2 V/ns (1 V/ns for each
signal). There are two sets of values listed: tDSa, tDHa and tDSb,
tDHb. The tDSa, tDHa values (for reference only) are equivalent
to the baseline values of tDS~, tDHb at VREF when the slew rate
is 2 V/ns, differentially. The baseline values, tDSb, DHb, are the
JEDEC-dened values, referenced from the logic trip points. tDSb
is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling
signal, while tDHb is referenced from VIL(DC) for a rising signal
and VIH(DC) for a falling signal. If the differential DQS slew rate
is not equal to 2 V/ns, then the baseline values must be derated
by adding the values from Tables 24 and 25 on pages 91–92. If
the DQS differential strobe feature is not enabled, then the DQS
strobe is single-ended, the baseline values are not applicable, and
timing is not referenced to the logic trip points. Single-ended DQS
data timing is referenced to DQS crossing VREF.
8.
tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specic voltage level, but specify when the device output is no
longer driving (when the device output is no longer driving (tHZ) or
begins driving (tLZ).
9.
This maximum value is derived from the referenced test load. tHZ
(MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.
Output
(VOUT)
Reference
Point
25
VTT = VCCQ/2
10.
tLZ (MIN) tLZ will prevail over a tDQSCK (MIN) + tRPRE (MAX)
condition.
11.
The intent of the Don’t Care state after completion of the
postamble is the DQS-driven signal should either be high, low or
High-Z and that any signal transition within the input switching
region must follow valid input requirements. That is if DQS
transitions high (above VIH DC (MIN) then it must not transition low
(below VIH (DC) prior to tDQSH (MIN).
12.
This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus turn
around.
13.
It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
HIGH during this time, depending on tDQSS.
14.
The refresh period is 64ms. This equates to an average refresh
rate of 7.8125s. However, a REFRESH command must be
asserted at least once every 70.3s or tRFC (MAX). To ensure
all rows of all banks are properly refreshed, 8192 REFRESH
commands must be issued every 64ms.
15.
Each half-byte lane has a corresponding DQS.
16.
CK and CK# input slew rate must be ≥ 1V/ns (≥ 2V/ns if measured
differentially).
17.
The data valid window is derived by achieving other specications
- tHP. (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window
derates in direct proportion to the clock duty cycle and a practical
data valid window can be derived.
18.
tHP (MIN) is the lesser of tCL minimum and tCH minimum actually
applied to the device CK and CK# inputs.
19.
READs and WRITEs with auto precharge are allowed to be
issued before tRAS (MIN) is satised since tRAS lockout feature is
supported in DDR2 SDRAM devices.
20.
VIL/VIH DDR2 overshoot/undershoot. REFER to the 512Mb or 1Gb
DDR2 SDRAM data sheet for more detail.
21.
tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already
an integer, round to the next highest integer. tCK refers to the
application clock period; nWR refers to the tWR parameter stored
in the MR[11,10,9]. Example: For 534 at tCK= 3.75 ns with tWR
programmed to four clocks. tDAL = 4 + (15 ns/3.75ns) clock = 4 +
(4) clocks = 8 clocks.
22.
The minimum READ to internal PRECHARGE time. This
parameter is only applicable when tRTP/2*tCK) > 1. If tRTP/2*tCK) ≤ 1,
then equation AL + BL/2 applies. Notwithstanding, tRAS (MIN) has
to be satised as well. The DDR2 SDRAM device will automatically
delay the internal PRECHARGE command until tRAS (MIN) has
been satised.
23.
Operating frequency is only allowed to change during self refresh
mode, precharge power-down mode, and system reset condition.
24.
ODT turn-on time tAON (MIN) is when the device leaves high
impedance and ODT resistance begins to turn on. ODT turn-on
time tAON (MAX) is when the ODT resistance is fully on. Both are
measured from tAOND.
25.
ODT turn-off time tAOF (MIN) is when the device starts to turn off
ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in
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