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參數(shù)資料
| 型號： | W3HG2256M72ACER534AD6MG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 512M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 296K |
| 代理商： | W3HG2256M72ACER534AD6MG |
W3HG2256M72ACER-AD6
ADVANCED
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
June 2007
Rev. 1
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
806
665
534
403
Units
ICC0
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
1,746
1,476
mA
ICC1
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD =
tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as ICC4W
TBD
2,016
1,926
1,836
mA
ICC2P
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
TBD
256
252
mA
ICC2Q
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
TBD
846
756
mA
ICC2N
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
TBD
936
846
mA
ICC3P
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
TBD
666
mA
Slow PDN Exit MRS(12) = 1
TBD
306
mA
ICC3N
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD
1,206
1,026
936
mA
ICC4W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
TBD
2,646
2,466
2,106
mA
ICC4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
TBD
2,646
2,466
2,106
mA
ICC5B
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
4,086
3,996
3,906
mA
ICC6
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
TBD
252
mA
ICC7
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the
following page for detailed timing conditions
TBD
5,256
5,076
4,896
mA
NOTES: ICC specs are based on
MICRON components. Other DRAM manufacturers parameters may be different.
Inactive chips are in ICC2P condition with inputs switching.
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| W3HG264M72EER403AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
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