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參數(shù)資料
| 型號(hào)： | W3HG232M64SEU806D4GG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.4 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SO-DIMM-200 |
| 文件頁(yè)數(shù)： | 11/13頁(yè) |
| 文件大小： | 154K |
| 代理商： | W3HG232M64SEU806D4GG |
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W3HG232M64SEU-D4
June 2007
Rev. 2
ADVANCED
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
COMPONENTS AC OPERATING CONDITIONS
AC Characteristics
Symbol
806
665
Units
Parameter
Min
Max
Min
Max
Clock Frequency
CL = 3
tCK
5858
ns
CL = 4
tCK
3.75
8
3.75
8
ns
CL = 5
tCK
3838
ns
CL = 6
tCK
2.5
8
-
ns
DQ output access time from CK / CK
tAC
-400
+400
-450
+450
ps
DQS output access time from CK / CK
DQSCK
–350
+350
-400
+400
ps
Average clock high pulse width
tCH.AVG
0.48
0.52
0.48
0.52
tCK.AVG
Average clock low pulse width
tCH.AVG
0.48
0.52
0.48
0.52
tCK.AVG
Average clock period
tCL.AVG
2500
8000
3000
8000
ps
DQ and DM input setup time
tDS.BASE
50
-
100
-
ps
DQ and DM input hold time
tDH.BASE
125
-
175
-
ps
Control & address input pulse width for each in
tACIPW
0.6
-
0.6
-
tCK.AVG
DQ and DM input pulse width for each input
tDIPW
0.35
-
0.35
-
tCK.AVG
Data-out high-impedance time from CK / CK
HZ
-tAC.MAX
ps
DQS/DQS low-impedance time from CK / CK
tLZ.DQS
tAC.MIN
tAC.MAX
tAC.MIN
tAC.MAX
ps
DQ low impedance time from CK/CK
tLZ.DQ
2x tAC.MIN
tAC.MAX
2x tAC.MIN
tAC.MAX
ps
DQS-DQ skew for DQS & associated DQ signals
tDQSQ
-
200
-
240
ps
CK half pulse width
tH
Min(
tCH.ABS,
tCL.ABS)
-
Min(
tCH.ABS,
tCL.ABS)
-ps
DQ hold skew factor
tQH
300
-
340
ps
DQ/DQS output hold time from DQS
tQH
tHP – tQH
-tHP – tQH
-ps
Write command to DQS associated clock edges
WL
RL-1
nCK
DQS latching rising transition to associated clock
edges
tDQSS
-0.25
+0.25
-0.25
+0.25
tCK.AVG
DQS input high pulse width
tDQSH
0.35
-
0.35
-
tCK.AVG
DQS input low pulse width
tDQSL
0.35
-
0.35
-
tCK.AVG
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
tCK.AVG
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
tCK.AVG
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK.AVG
Write preamble
tWPRE
0.35
-
0.35
-
tCK.AVG
Address and control input setup time
tIS.BASE
175
-
200
ps
Address and control input hold time
tIH.BASE
250
-
275
-ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK.AVG
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK.AVG
CAS to CAS command delay
tCCD
2-2-
nCK
Note:
AC specication is based on
QIMONDA components. Other DRAM manufactures specication may be different.
Continued on next page
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相關(guān)代理商/技術(shù)參數(shù) |
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| W3HG264M72EER403AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER534AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER665AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER806AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER-AD7 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
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