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參數(shù)資料
| 型號： | W3HG64M72EER403AD7SG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.6 ns, ZMA244 |
| 封裝： | ROHS COMPLIANT, DIMM-244 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 256K |
| 代理商： | W3HG64M72EER403AD7SG |
W3HG64M72EER-AD7
October 2006
Rev. 2
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION (Continued)
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Notes
Data
Strobe
DQS read preamble
tRPST
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
35
DQS write preamble setup time
tWPRES
TBD
000
ps
12, 13,
36
DQS write preamble
tWPRE
TBD
0.35
0.25
tCK
DQS write postamble
tWPST
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
11
Write command to rst DQS
latching transition
tDQSS
TBD
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
tCK
Command
and
Address
Address and control input
pulse width for each input
tIPW
TBD
0.6
tCK
Address and control input
setup time
tISa
TBD
400
500
600
ps
6, 21
Address and control input
hold time
tIHa
TBD
400
500
600
ps
6, 21
Address and control input
setup time
tISb
TBD
200
250
350
ps
6, 21
Address and control input
hold time
tIHb
TBD
275
375
475
ps
6, 21
CAS# to CAS# command
delay
tCCD
TBD
222
tCK
Active to Active (same bank)
command
tRC
TBD
55
ns
33
Active bank a to Active b bank
command
tRRD
TBD
7.5
ns
27
Active to Read or Write delay
tRCD
TBD
15
ns
Four Bank Activate period
tFAW
TBD
37.5
ns
30
Active to precharge command
tRAS
TBD
40
70,000
40
70,000
40
70,000
ns
20, 33
Internal Read to precharge
command delay
tRTP
TBD
7.5
ns
23, 27
Write recovery time
tWR
TBD
15
ns
27
Auto precharge wirte recovery
and precharge time
tDAL
TBD
tWR+tRP
ns
22
Interval Write to Read
command delay
tWTR
TBD
10
7.5
10
ns
27
Precharge command period
tRP
TBD
15
ns
31
Precharge All command period
tRPA
TBD
tRP+tCK
ns
31
Load Mode command cycle
time
tMRD
TBD
222
tCK
CKE low to CK,CK#
uncertainty
tDELAY
TBD
tIS+tCK+tIH
ns
28
NOTE:
AC specication is based on
MICRON components. Other DRAM manufactures specication may be different.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3HG64M72EER403AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG64M72EER534AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG64M72EER665AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG64M72EER806AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG64M72EER-AD7 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
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