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參數(shù)資料
| 型號： | W49F002UP90BN |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 256K X 8 FLASH 5V PROM, 90 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 30/30頁 |
| 文件大?。?/td> | 0K |
| 代理商： | W49F002UP90BN |
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W49F002U
Publication Release Date: April 19, 2005
- 9 -
Revision A7
completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 –
DQ6 may be still invalid. The valid data on DQ0
DQ7 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out (see "Command Definitions").
See " #DATA Polling During Embedded Algorithm Timing Diagrams".
6.4.2 DQ6: Toggle Bit
The W49F002U also features the "Toggle Bit" as a method to indicate to the host system that the
embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling)
data from the device at any address will result in DQ6 toggling between one and zero. Once the
Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be
read on the next successive attempt. During programming, the Toggle Bit is valid after the rising edge
of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the
rising edge of the sixth #WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is
valid after the last rising edge of the sector erase #WE pulse. The Toggle Bit is active during the sector
erase time-out.
7. TABLE OF OPERATING MODES
7.1
Device Bus Operations
PIN
MODE
#CE
#OE
#WE
#RESET
A0
A17
DQ0
DQ7
Read
VIL
VIH
Ain
Dout
Write
VIL
VIH
VIL
VIH
Ain
Din
VIH
X
VIL
X
High Z/DOUT
Write Inhibit
VIH
X
VIH
X
High Z/DOUT
Standby
VIH
X
VIH
X
High Z
Output Disable
VIL
VIH
X
High Z
Reset
X
VIL
X
High Z
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