參數(shù)資料
型號(hào)： W65C134SQ-8
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁數(shù)： 18/60頁
文件大小： 711K
代理商： W65C134SQ-8
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
13
When writing to the Transmitter in seven bit mode, bit 7 is discarded. When reading
from the receive data register during seven bit mode, bit 7 is always zero. When
ACSR2=1, the Transmitter and Receiver send and receive 8-bit data. The Transmitter
sends 11 bits of information (one start, 8 data, one parity and one stop or two stop bits).
The Receiver receives 10 or 11 bits of information (one start, 8 data, one stop or one
parity and one stop bit). A RESET clears ACSR2.
Parity Enable. When ACSR3=0, parity is disabled. A RESET clears ACSR3. When
ACSR3=1, parity is enabled for both the Transmitter and Receiver.
Odd or Even Parity. When ACSR4=0 and parity is enabled, then Odd parity is
generated where the number of ones is the data register plus parity bit equal an odd
number of "1's". When ACSR4=1 and parity is enabled, then Even parity is generated
where the number of ones in the data register plus parity bit equal an even number of
"1's". ACSR4 is cleared by Reset.
Receiver Enable. The Asynchronous Receiver is enabled when ACSR5=1. A RESET
clears ACSR5. When ACSR5=1 the Receiver is enabled and Receiver Interrupts occurs
anytime the contents of the Receiver shift register contents are transferred to the
Receiver Data Register. The Receiver Interrupt is cleared when the Receive Data
Register is read ($0023). The Receive data, RxD, is enabled on P60 when ACSR5=1.
When ACSR5=0, all Receiver operation is disabled and all Receive logic is cleared, the
Receiver data register bits 0-6 are not affected and bit 7 is cleared.
Software Semaphore. ACSR6 may be used for communications among routines which
access the UART. This bit has no effect on the UART operation and is cleared upon a
RESET. This signal can be thought of as a manually set “busy” signal.
Receiver Error Flag. The Receiver logic detects three possible error conditions and sets
ACSR7: parity, framing or over-run. A parity error occurs when the parity bit received
does not match the parity generated on the receive data. A framing error occurs when
the stop bit time finds a "0" instead of a "1". An over-run occurs when the last data in
the Receiver Data Register has not been read and new data is transferred from the
Receive Shift Register. ACSR7 is cleared by a RESET or upon writing a "1" to
ACSR7. Writing a "0" to ACSR7 has no effect on ACSR7.
ACSR3:
ACSR4:
ACSR5:
ACSR6:
ACSR7:
ACSR ($0022)
7
6
5
4
3
2
1
0
Transmitter Enable
Transmitter Interrupt Source
Select
Seven or Eight Bit Data Select
Parity Enable
Odd or Even Parity Select
Receiver Enable
Software Semiphore
Receiver Error Flag
Figure 1-9 ACSR Bit Assignments
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