參數(shù)資料
型號(hào)： W65C832PL-6
元件分類(lèi)： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁(yè)數(shù)： 17/62頁(yè)
文件大?。?/td> 891K
代理商： W65C832PL-6
WESTERN DESIGN CENTER
W65C816S
March 1, 2000
17
2.9
Non-Maskable Interrupt (NMIB)
A negative transition on the NMIB input initiates an interrupt sequence. A high-to-low transition initiates an
interrupt sequence after the current instruction is completed. The Wait for Interrupt (WAI) instruction may be
executed to ensure that the interrupt will be recognized immediately. The Non-Maskable Interrupt vector address
is 00FFFA,B (Emulation mode) or 00FFEA,B (Native mode). Since NMIB is an edge-sensitive input, an
interrupt will occur if there is a negative transition while servicing a previous interrupt. Also, no interrupt will
occur if NMIB remains low. The NMIB signal going low causes 3 bytes of information to be pushed onto the
stack before jumping to the interrupt handler. The first byte is the high byte in the Program Counter. The second
byte is the Program Counter low byte. The third byte is the status register valve. These valves are used to return
the processor to it's original state prior to the NMI interrupt.
2.10
Phase 2 In (PHI2)
This is the system clock input to the microprocessor internal clock generator (equivalent to PHI0(IN) on the
6502). During the low power Standby Mode, PHI2 can be held in either state to preserve the contents of internal
registers.
2.11
Read/Write (RWB)
When the RWB output signal is in the high state, the microprocessor is reading data from memory or I/O. When
in the low state, the Data Bus contains valid data from the microprocessor which is to be stored at the addressed
memory location. When using the W65C816S, the RWB signal may be set to the high impedance state by Bus
Enable (BE).
2.12
Ready (RDY)
This bi-directional signal indicates that a Wait for Interrupt (WAI) instruction has been executed allowing the
user to halt operation of the microprocessor. A low input logic level will halt the microprocessor in its current
state. Returning RDY to the active high state allows the microprocessor to continue following the next Phase 2 In
Clock negative transition. The RDY signal is internally pulled low following the execution of a Wait for
Interrupt (WAI) instruction, and then returned to the high state when a RESB, ABORTB, NMIB, or IRQB
external interrupt is provided. This feature may be used to eliminate interrupt latency by placing the WAI
instruction at the beginning of the IRQB servicing routine. If the IRQB Disable flag has been set, the next
instruction will be executed when the IRQB occurs. The processor will not stop after a WAI instruction if RDY
has been forced to a high state. The Stop (STP) instruction has no effect on RDY. The RDY pin has an active
pull-up. When outputting a low level, the pull-up is disabled. The RDY pin can still be wired ORed.
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