參數(shù)資料
型號(hào)： W65C832PL-6
元件分類： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁(yè)數(shù)： 20/62頁(yè)
文件大?。?/td> 891K
代理商： W65C832PL-6
WESTERN DESIGN CENTER
W65C816S
March 1, 2000
20
The following addressing mode descriptions provide additional detail as to how effective addresses are
calculated. Twenty-four addressing modes are available for the W65C816S.
3.5.1
The operand is the second byte (second and third bytes when in the 16-bit mode) of the instruction.
Immediate Addressing-#
3.5.2
With Absolute addressing the second and third bytes of the instruction form the low-order 16 bits of the effective
address. The Data Bank Register contains the high-order 8 bits of the operand address.
Absolute-a
Instruction:
Operand
OpCode
DBR
addrl
addrh
addrh
addrl
3.5.3
The second, third and fourth byte of the instruction form the 24-bit effective address.
Absolute Long-al
Instruction:
Operand Address:
OpCode
baddr
addrl
addrh
addrh
addrl
baddr
3.5.4
The second byte of the instruction is added to the Direct Register (D) to form the effective address. An additional cycle
is required when the Direct Register is not page aligned (DL not equal 0). The Bank register is always 0.
Direct-d
Instruction:
OpCode
offset
Direct Register
+
offset
Operand Address:
00
effective address
3.5.5
This form of addressing always uses a single byte instruction. The operand is the Accumulator.
Accumulator-A
3.5.6
Implied addressing uses a single byte instruction. The operand is implicitly defined by the instruction.
Implied-i
3.5.7
This address mode is often referred to as Indirect,Y. The second byte of the instruction is added to the Direct Register
(D). The 16-bit contents of this memory location is then combined with the Data Bank register to form a 24-bit base
address. The Y Index Register is added to the base address to form the effective address.
Direct Indirect Indexed-(d),y
Instruction:
OpCode
offset
Direct Register
+
offset
00
(direct address)
then: +
DBR
base address
+
Operand Address:
Y Reg
effective address
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