參數(shù)資料
型號： W6692ACD
廠商： WINBOND ELECTRONICS CORP
元件分類： 數(shù)字傳輸電路
英文描述： DATACOM, ISDN CONTROLLER, PQFP100
封裝： LQFP-100
文件頁數(shù)： 23/98頁
文件大小： 584K
代理商： W6692ACD
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-3 -
TABLE OF CONTENTS
1. GENERAL DESCRIPTION................................................................................................................................................. 8
2. FEATURES............................................................................................................................................................................ 8
3. PIN CONFIGURATION ..................................................................................................................................................... 9
4. PIN DESCRIPTION........................................................................................................................................................... 12
5
. SYSTEM DIAGRAM AND APPLICATIONS ................................................................................................................ 15
6. BLOCK DIAGRAM ........................................................................................................................................................... 16
7. FUNCTIONAL DESCRIPTIONS..................................................................................................................................... 17
7.1 MAIN BLOCK FUNCTIONS................................................................................................................................................... 17
7.2 LAYER 1 FUNCTIONS DESCRIPTIONS ................................................................................................................................... 18
7.2.1 S/T Interface Transmitter/Receiver ............................................................................................................................ 18
7.2.2 Receiver Clock Recovery And Timing Generation...................................................................................................... 22
7.2.3 Layer 1 Activation/Deactivation ................................................................................................................................ 22
7.2.3.1 States Descriptions And Command/Indication Codes .......................................................................................... 22
7.2.3.2 State Transition Diagrams................................................................................................................................... 24
7.2.4 D Channel Access Control ......................................................................................................................................... 28
7.2.5 Frame Alignment ....................................................................................................................................................... 28
7.2.5.1 FAinfA_1fr ......................................................................................................................................................... 29
7.2.5.2 FAinfB_1fr ......................................................................................................................................................... 29
7.2.5.3 FAinfD_1fr ......................................................................................................................................................... 29
7.2.5.4 FAinfA_kfr ......................................................................................................................................................... 29
7.2.5.5 FAinfB_kfr ......................................................................................................................................................... 29
7.2.5.6 FAinfD_kfr ......................................................................................................................................................... 30
7.2.5.7 Faregain.............................................................................................................................................................. 30
7.2.6 Multiframe Synchronization....................................................................................................................................... 30
7.2.7 Test Functions ........................................................................................................................................................... 31
7.3 SERIAL INTERFACE BUS ..................................................................................................................................................... 33
7.4 B CHANNEL SWITCHING .................................................................................................................................................... 33
7.6 D CHANNEL HDLC CONTROLLER...................................................................................................................................... 35
7.6.1 D Channel Message Transfer Modes.......................................................................................................................... 36
7.6.2 Reception of Frames in D Channel ............................................................................................................................ 36
7.6.3 Transmission of Frames in D Channel ....................................................................................................................... 37
7.7 B CHANNEL HDLC CONTROLLER ...................................................................................................................................... 38
7.7.1 Reception of Frames in B Channel ...................................................................................................................... 38
7.7.2 Transmission of Frames in B Channel........................................................................................................................ 39
7.8 GCI MODE SERIAL INTERFACE BUS.................................................................................................................................... 40
7.8.1 GCI Mode C/I0 Channel Handling ............................................................................................................................ 41
7.8.2 GCI Mode Monitor Channel Handling....................................................................................................................... 41
7.9 PCI/MP INTERFACE CIRCUIT ............................................................................................................................................. 42
7.9.1 PCI Slave Mode And Configuration Serial EEPROM ................................................................................................ 42
7.9.2 8-bit Microprocessor Interface .................................................................................................................................. 44
7.10 PERIPHERAL CONTROL..................................................................................................................................................... 44
8. REGISTER DESCRIPTIONS ............................................................................................................................................. 46
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