參數(shù)資料
型號(hào)： W6694A
英文描述： TE Mode S/T Controller with USB 1.1 Interface
中文描述： TE模S / T的與USB 1.1接口控制器
文件頁(yè)數(shù)： 26/42頁(yè)
文件大?。?/td> 567K
代理商： W6694A
Preliminary Data Sheet
W6694A USB-ISDN S/T-Controller
Write
Address 01h
-26-
Publication Release Date: May, 2001
Revision 1.03
8.2.2 Command Register 1
Value after reset: 00h
Writing 1 to the following bits will activate each corresponding function. Writing 0 to these bits has no effect.
7
6
5
4
3
DXRST
DRRST
DXEN
DREN
SRST
DXRST D Channel Transmitter Reset
Setting this bit resets D channel transmitter, and clear transmit FIFO (XFIFO). The transmitter will immediately
transmit inter frame time fill pattern (all 1’s) to D channel in ISDN layer 1, but the XFIFO is disabled (not active).
Software must issue DXEN to enable (activate) D channel XFIFO. After reset is done, this bit becomes 0. If this bit
and DXEN bit are set at the same time, the reset action will be performed first and completed, then DXEN actions
will follow.
DRRST D Channel Receiver Reset
Setting this bit resets D channels receiver, and clear receive FIFO (RFIFO). The D channels is disabled (not active).
Software must issue DREN to enable (activate) D channel RFIFO, in order to receive D channel data from ISDN,
and send data to USB. After reset is done, this bit becomes 0. If this bit and DREN bit are set at the same time, the
reset action will be performed first and completed, then other actions will follow.
DXEN D Channel Transmit FIFO Enable
Setting this bit enables D channel transmit FIFO (XFIFO). After enabled, the D channel XFIFO will begin to
receive D channel data from USB, and send data to ISDN. After enabled, this bit becomes 0.
DREN D Channel Receive FIFO Enable
Setting this bit enables D channel receive FIFO (RFIFO). After enabled, the D channel RFIFO will begin to receive
D channel data from ISDN, and send data to USB. After enabled, this bit becomes 0.
SRST Software Reset
Setting this bit internally generates a software-reset signal. The effect of this reset signal is equivalent to hardware-
reset pin, except that the USB circuit and all USB configured data are not reset. This bit must be set along, i.e., all
other bits in this register must not set at the same time. This bit is not auto-clear, once this bit is set to 1, software
must write 0 to this bit to exit from the reset mode. In the reset-mode the chip will not function properly.
CISOE Clear Isochronous-OUT Error
Setting this bit clears error-indication bit ISOE indicating Isochronous-OUT error. The ISOE bit is carried by
Isochronous-IN packet. After cleared, this bit becomes 0.
DLP
Digital Loop back
Setting this bit activates the digital loop back function. The transmitted digital 2B+D channels are looped to the
received 2B+D channels. Note that after hardware reset, the internal clocks will turn off if the S bus is not connected
or if there is no signal on the S bus. In this case, the C/I command ECK (value 0) must be issued through register
CIX to enable loop back function.
This bit remains set, until cleared by software reset (SRST).
RLP
Remote Loop back
CMDR1
2
1
0
CISOE
DLP
RLP
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