參數(shù)資料
型號(hào)： W6694A
英文描述： TE Mode S/T Controller with USB 1.1 Interface
中文描述： TE模S / T的與USB 1.1接口控制器
文件頁數(shù)： 38/42頁
文件大?。?/td> 567K
代理商： W6694A
Preliminary Data Sheet
W6694A USB-ISDN S/T-Controller
-38-
Publication Release Date: May, 2001
Revision 1.03
Note 1:
These drawings are not to scale.
Note 2 :
The frequency of PBCK is 1536 kHz which includes 24 channels of 64 kbps data. The PFCK1 and PFCK2 are
located at channel 1 and channel 2, each with a 8 x PBCK duration.
Detailed PCM timing
Parameter
Parameter Descriptions
Min.
ta1
PBCK pulse high
ta2
PBCK pulse low
195
ta3
Frame clock asserted from
PBCK
ta4
PTXD data delay from PBCK
ta5
Frame clock deasserted from
PBCK
ta6
PTXD hold time from PBCK
10
ta7
PRXD setup time to PBCK
20
ta8
PRXD hold time from PBCK
10
Note:
The PCM clocks are locked to the S/T receive clock. At every two or three PCM frame time (125
μ
s), PBCK and
PFCK1, PFCK2 may be adjusted by one local oscillator cycle (130 ns) in order to synchronize with S/T clock. This shift is
made on the LOW level time of PBCK and the HIGH level time is not affected. This introduces jitters on the PBCK, PFCK1
and PFCK2 with jitter amplitude 260 ns (peak-to-peak) and jitter frequency about 2.67~4 kHz.
Nominal
325
325
Max.
455
20
Remarks
Unit = ns
20
20
PBCK
PFCK1
PFCK2
PTXD
PRXD
ta1
ta2
ta3
ta4
ta5
ta6
ta7
ta8
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