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參數(shù)資料
| 型號： | W6694ACD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DATACOM, ISDN CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 |
| 文件頁數(shù)： | 17/42頁 |
| 文件大?。?/td> | 567K |
| 代理商： | W6694ACD |
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Preliminary Data Sheet
W6694A USB-ISDN S/T-Controller
-24-
Publication Release Date: May, 2001
Revision 1.03
8. REGISTER DESCRIPTIONS
All registers can be controlled from USB endpoints, as described in previous sections.
8.1 Interrupt Registers
These registers will be read by Interrupt-IN packet only, so the USB host will periodically receive these data. These registers
can not be read by Bulk-IN transfer.
8.1.1 Interrupt Status Register
ISTA
Read_clear
This register indicates interrupt occurred in various interrupt sources. This register is cleared automatically after it is read
and successfully ACKed by the USB host.
Values after reset: 00h
7
6
5
4
3
2
1
0
ICC
MOC
PIOIC
EPAC
0
ICC
Layer 1 Indication Code Change
A change of value in the received indication code has been detected.
The new code is in Layer 1
Command/Indication Register (CIR) register.
MOC
Monitor Channel Status Change
A change of value in the GCI mode Monitor Channel Interrupt Register (MOIR) has occurred.
PIOIC Programmable IO Port Input Signal Changed
A change of value in at least one input IO pin is detected. The input IO pins that change value can be identified in
PIO Input Change Register (PICR) register.
EPAC EEPROM Access Completed
The most recent EEPROM access (read/write) operation is completed. If it was a read operation, the data is already
stored in register EPRDL and EPRDH.
8.1.2 Layer 1 Command/Indication Register
CIR
Read
Value after reset: 0Fh
7
6
5
4
3
2
1
0
CIR3
CIR2
CIR1
CIR0
CIR3-0 Layer 1 Indication Code
Value of the received layer 1 indication code for S/T interface. Note these bits have a buffer size of two.
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