參數(shù)資料
型號： W72M64VK-XBX
英文描述： 2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package
中文描述： 2Mx64 3.3V的同時(shí)閃電行動多芯片封裝
文件頁數(shù)： 10/16頁
文件大?。?/td> 568K
代理商： W72M64VK-XBX
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W72M64VK-XBX
April 2005
Rev. 0
FIGURE 9: BACK TO BACK READ/WRITE CYCLE TIMINGS
FIGURE 10: DATA POLLING TIMINGS (DURING EMBEDDED ALGORITHMS)
Addresses
CS#
OE#
WE#
Data
t
AH
Valid RA
Valid PA
Valid PA
Valid PA
t
WC
t
RC
t
ACC
t
CE
t
WP
t
DH
t
WC
t
WC
t
CPH
t
CP
t
OE
t
WPH
t
OEH
t
GHWL
t
DF
Valid In
Valid In
t
DS
t
OH
t
SR/W
Valid Out
Valid In
WE# Controlled Write Cycle Read Cycle CS# Controlled Write Cycle
Addresses
VA
VA
VA
t
RC
CS#
Complement
Complement
True
DQ
0
-DQ
6
t
CE
t
CH
t
OE
OE#
WE#
t
OEH
t
DF
t
OH
Valid Data
High Z
RY/BY#
t
BUSY
DQ
7
t
ACC
Status Data
Status Data
True
Valid Data
High Z
NOTE:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
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