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W741C250
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0
1
2
SEF
w
w
w
w
3
Note: W means write only.
SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0.
SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1.
SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2.
SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3.
Hold Mode Release Condition Flag (HCF)
The hold mode release condition flag is organized as an 8-bit binary register (HCF0 to HCF7). It
indicates by which interrupt source the hold mode has been released, and it is loaded by hardware.
The HCF can be read out by the MOVA R, HCFL
and MOVA R, HCFH instructions. When any of the
HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be
reset by the CLR EVF, #I (EVF.n = 0) or MOV HEF, #I (HEF.n = 0) instructions. When EVF or HEF
has been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as
follows:
0
1
2
3
4
5
6
7
R
R
HCF
R
R
R
Note: R means read only.
HCF.0 = 1 Hold mode was released by overflow from Divider 0.
HCF.1 = 1 Hold mode was released by underflow from Timer 0.
HCF.2 = 1 Hold mode was released by a signal change on port RC.
HCF.3 Reservsd
HCF.4 = 1 Hold mode was released by a falling edge signal on the
INT
pin.
HCF.5 = 1 Hold mode was released by underflow from Timer 1.
HCF.6 & HCF.7 are reserved.
Event Flag (EVF)
The event flag is organized as a 8-bit binary register (EVF0 to EVF7). It is set by hardware and reset
by the CLR EVF, #I instruction or the occurrence of an interrupt. The bit descriptions are as follows:
EVF
0
1
2
3
4
5
R
R
R
R
R
6
7
Note: R means read only.
EVF.0 = 1 Overflow from Divider 0 occurred.
EVF.1 = 1 Underflow from Timer 0 occurred.
EVF.2 = 1 Signal change on port RC occurred.