- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄245684 > W78M64VP110SBI (WHITE ELECTRONIC DESIGNS CORP) SPECIALTY MEMORY CIRCUIT, PBGA156 PDF資料下載
參數(shù)資料
| 型號(hào)： | W78M64VP110SBI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA156 |
| 封裝： | 13 X 22 MM, PLASTIC, BGA-156 |
| 文件頁數(shù)： | 23/48頁 |
| 文件大?。?/td> | 1548K |
| 代理商： | W78M64VP110SBI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
October 2008
Rev. 2
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
GENERAL DESCRIPTION
The W78M64VP-XSBX is a 512Mb, 3.3 volt-only Page
Mode memory device.
The device offers fast page access times allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has separate chip
enable (CS#), write enable (WE#) and output enable (OE#)
controls.
The device offers uniform 64 Kword (128Kb) Sectors:
Page Mode Features
The page size is 8 words. After initial page access is
accomplished, the page mode operation provides fast read
access speed of random locations within that page.
Standard Flash Memory
Features
The device requires a 3.3 volt power supply for both read
and write functions. Internally generated and regulated
voltages are provided for the program and erase operations
Page Mode Features
The page size is 8 words. After initial page access is
accomplished, the page mode operation provides fast read
access speed of random locations within that page.
Device Operations
This section describes the read, program, erase,
handshaking, and reset features of the Flash devices.
Operations are initiated by writing specic commands or
a sequence with specic address and data patterns into
the command registers ( see Table 38 and table 39). The
command register itself does not occupy andy addressable
memory location; rather, it is composed of latches that store
the commands, along with the address and data information
needed to execute the command. The contents of the
register serves as input to the internal state machine and
the state machine outputs dictate the function of the device.
Writing incorrect address and data values or writing them in
an improper sequence may place the device in an unknown
state, in which case the system must pull the RESET# pin
low or power cycle the device to return the device to the
reading array data mode.
Device Operation Table
The device must be setup appropriately for each operation.
Table 2 describes the required state of each control pin for
any particular operation.
VersatileIOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to
set the voltage levels that the device generates and tolerates
on all inputs and outputs (address, control, and DQ signals).
VIO range is 1.65 to VCC.
For example, a VIO of 1.65-3.6 volts allows for I/O at the
1.8 or 3 volt levels, driving and receiving signals to and from
other 1.8 or 3 V devices on the same data bus.
Read
All memories require access time to output array data. In a
read operation, data is read from one memory location at
a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes
the data on its outputs to arrive with the address on its
inputs.
The device defaults to reading array data after device power-
up or hardware reset. To read data from the memory array,
the system must rst assert a valid address on Amax-A0,
while driving OE# and CE# to VIL. WE# must remain at
VIH. All addresses are latched on the falling edge of CE#.
Data will appear on DQ15-DQ0 after address access time
(tACC), which is equal to the delay from stable addresses
to valid output data.
The OE# signal must be driven to VIL. Data is output on
DQ15-DQ0 pins after the access time (tOE) has
elapsed from the falling edge of OE#, assuming the tACC
access time has been meet.
Page Read Mode
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random
locations within a page. The page size of the device is 8
words/16 bytes. The appropriate page is selected by the
higher address bits A(max)-A3.
Address bits A2-A0 in word mode (A2 to A-1 in byte
mode) determine the specic word within a page. The
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WS-128K32-85G4M | 512K X 8 MULTI DEVICE SRAM MODULE, 85 ns, CQFP68 |
| WF128K32A-150HM | 512K X 8 FLASH 12V PROM MODULE, 150 ns, CHIP66 |
| WS32K32-35HM | 128K X 8 MULTI DEVICE SRAM MODULE, 35 ns, CHIP66 |
| WS32K32N-100HSI | 128K X 8 MULTI DEVICE SRAM MODULE, 100 ns, CHIP66 |
| WS32K32N-25HSM | 128K X 8 MULTI DEVICE SRAM MODULE, 25 ns, CHIP66 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W78M64VP110SBM | 制造商:Microsemi Corporation 功能描述:8MX64 FLASH 3.3V PAGE MODE - Bulk |
| W78M64V-XSBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash MCP |
| W78NCSX-23 | 功能描述:低信號(hào)繼電器 - PCB 4PDT 3A 24VDC IND RoHS:否 制造商:NEC 觸點(diǎn)形式:2 Form C (DPDT-BM) 觸點(diǎn)電流額定值: 線圈電壓:5 V 最大開關(guān)電流:1 A 線圈電流:1 A 線圈類型:Non-Latching 功耗:140 mW 端接類型:SMT 絕緣: 介入損耗: |
| W78PCX-1 | 制造商:Magnecraft 功能描述: |
| W78PCX-2 | 制造商:Magnecraft 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。