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參數(shù)資料
| 型號(hào)： | W812 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 99K |
| 代理商： | W812 |
I
W812 IEEE 1394 Link Layer Controller
I
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
4
Oki Semiconductor
SIGNAL DESCRIPTIONS
PHY-Link Interface
Signal
Type
Assertion
Description
Lclk
In
—
50-MHz SCLK from PHY.
AnxJLReg
Out
—
LINK request port to PHY. Used to make bus requests or accesses to PHY.
Ctlln
In
—
Input from Bi-di control port for bi-directional pins.
CtlOut
Out
—
Output to Bi-di control port for bi-directional pins.
CtlTriEnb
Out
HIGH
Tri-state enable to Bi-di control port.
AnxJDin
In
—
Input from Bi-di data port. Used to exchange data with PHY.
AnxJDout
Out
—
Output to Bi-di data port. Used to exchange data with PHY.
DataTriEnb
Out
HIGH
Tri-state enable to Bi-di data port.
Direct
In
HIGH
Indicates LINK and PHY are directly connected, rather than through an isolation barrier.
LinkPowerOn
Out
HIGH
Indicates LINK is powered on.
Application Bus Interface
Signal
Type
Assertion
Description
DPBdata
Bi-di
—
Data Path Data Bus.
Used to exchange data with other application modules.
DPBdrive
Out
HIGH
Indicates W812 is driving DPBdata.
DPBValid
Bi-di
HIGH
Indicates the quality description of DPBdata.
DPBValid_en
Out
HIGH
Enable to DPBValid signal
DPBFifoStatus
In
—
Indicates the FIFO status for fetches and stores by FIFO controller, such as Oki’s W812-F.
DPBadr
Bi-di
—
Data Path Bus Address
. Specifies the DPBus transfer.
DPBadr_en
Out
HIGH
Enables to DPBadr signals.
DPBWrite
Bi-di
HIGH
Specifies whether the DPBus transfer is a read or write.
DPReqLink
Out
HIGH
DPBus request line for LINK.
DPReqWrLink
Out
HIGH
DPBus request operation type line for LINK.
DPAckLink
In
HIGH
DPBus request grant line to LINK.
DPStallLink
Out
HIGH
LINK indication of need to extend current DPBus cycle.
DPBWait
In
HIGH
Indicates the DPBus operation is to be extended a cycle.
MasterReset
In
HIGH
Initializes the whole module. It is a synchronous reset, clocked by Lclk.
Isochronous Control Interface
Signal
Type
Assertion
Description
CycleIn
In
—
8-kHz clock to optionally indicate isochronous cycle.
CycleOut
Out
—
20-ns pulse to indicate the start of an isochronous cycle.
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