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參數(shù)資料
| 型號(hào)： | W812 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 99K |
| 代理商： | W812 |
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I
W812 IEEE 1394 Link Layer Controller
I
5
Oki Semiconductor
FUNCTIONAL DESCRIPTION
The W812 controller has three basic interfaces:
Application Bus
PHY-Link
Isochronous Control
The Application Bus and Isochronous Control interfaces are application interfaces; whereas, the Link-
PHY interface conforms to the IEEE 1394-1995 Standard (as described in Annex J section) and provides
an industry standard interface to the PHY. The Application Bus interface provides a highly efficient inter-
face to other application modules including the FIFO controller. Oki also provides an optional W812-F
FIFO controller which is ready to interface with the W812.
Functional Modules
Data Path Interface (DPIF)
This block interfaces with Oki’s high performance application bus which is a multi-drop multiple master
bus that uses a streamlined, 3-phase protocol. W812 uses this interface to communicate with the applica-
tion modules and necessary FIFO controller. Oki’s bus interface is simple and relatively inexpensive in
terms of pin and interface count. Yet the W812 has good bandwidth of ~200 MBps and a low and predict-
able latency. Oki’s optional W812-F FIFO controller also uses this busing scheme to provide an overall
high performance 1394 Link Layer solution.
Asynchronous Transfer Request
This block queues requests for asynchronous transmission by fetching all the necessary parameters to the
transmitter and receiver.
Isochronous Transfer Request
This block queues requests for isochronous transmission by fetching all the necessary parameters to the
transmitter and receiver.
Read-Write Request
This block queues read and write requests to the PHY register through the Annex J request block and for-
mats and fetches request packets to the Annex J Request Block.
Annex J Request
This block generates the Annex J Request to the PHY. When more than one request is queued at the same
time, this block prioritizes the queued requests.
Transmitter and Receiver
This block generates the flow control signals for the W812 and determines when, what, where, and how
a packet is fetched during transmission and stored during reception. This block performs the following
functions:
Format appropriate packets
Cycle monitor
Cycle master
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