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參數(shù)資料
| 型號(hào)： | W83194BR-P4X |
| 英文描述： | Step-less VIA P4X/P4M Main Clock Gen. |
| 中文描述： | 步少威盛P4X/P4M主時(shí)鐘創(chuàng) |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 731K |
| 代理商： | W83194BR-P4X |
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W83194BR-250
4.1 Crystal I/O
SYMBOL
PIN
I/O
FUNCTION
Xin
3
IN
Crystal input with internal loading capacitors(36pF)
and feedback resistors.
Xout
4
OUT
Crystal output at 14.318MHz nominally with internal
loading capacitors(36pF).
4.2 CPU, AGP,PCI,IOAPIC Clock Outputs
SYMBOL
PIN
I/O
FUNCTION
CPUCLK_F , [1:3]
42,39,38,35
OUT
Low skew (< 250ps) clock outputs for host
frequencies such as CPU and Chipset.
CPUCLK_F is the free running pin and does not
affect by CPU_STOP#
CPU_STOP# when driven low.
Pin9 *Mode1=1, PCI_STOP# when driven low.
Pin9 *Mode1=0, RESET# output (4ms low active
pulse when Watch Dog time out)
Power Down mode when driven low.
Clock outputs synchronous with PCI clock and
powered by VddLAPIC.
3.3V 33MHz free running PCI clock during normal
operation. Latched input for Mode1* at initial power
up for pin34 selection.
*Mode1=1, pin 34 =CPU_STOP# when driven low.
*Mode1=0, pin 34 = RESET# output (4ms low active
pulse when Watch Dog time out)
Low skew (< 250ps) PCI clock outputs.
CPU_STOP#
PCI_STOP#/RESET$
34
33
IN
I/O
PD#
IOAPIC[0:1]
PCICLK_F/Mode1*
32
45,44
IN
OUT
9
I/O
PCICLK[1:8]
10,11,12,13,14
,16,17,18,20
23,26,27
21,22
OUT
AGP [0:2]
*FS[1:0]
OUT
IN
3.3V output clocks for the chipset.
H/W selecting the output frequency of CPU, AGP and
PCI clocks (Default=1).
Publication Release Date:April. 2002
- 4 - Revision 1.0
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