參數(shù)資料
型號(hào): W83196R-718
英文描述: VIA Buffer Chip(4*DDR or 2*DDR + 3*SDRAM)
中文描述: 威盛緩沖芯片(4 * DDR或2 * 3 *的DDR SDRAM內(nèi)存)
文件頁數(shù): 8/13頁
文件大小: 731K
代理商: W83196R-718
W83194BR-250
6.2.4 Register 3: 24MHz, 48MHz Clock Register ( 1 = enable, 0 = Stopped )
Bit
7
6
@PowerUp
0
0
Pin
-
-
Description
1 = ±0.25% ,0=±0.5% Spread Spectrum Modulation
SEL24_48 (0=24Mhz, 1=48MHz)
5
1
6
48MHz (Active / Inactive)
4
3
1
1
1
7
9
27
26
23
24_48MHz (Active / Inactive)
PCICLK_F (Active / Inactive)
2
1
0
AGP2 (Active / Inactive)
AGP1 (Active / Inactive)
AGP0 (Active / Inactive)
1
1
6.2.5 Register 4: Buffer Chip Register (1 = enable, 0 = Stopped)
Bit
@PowerUp
Pin
Description
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved for W83176R-251
Reserved for W83176R-251
Reserved for W83176R-251
Reserved for W83176R-251
Reserved for W83176R-251
Reserved for W83176R-251
Reserved for W83176R-251
Reserved for W83176R-251
6.2.6 Register 5: Buffer Chip Register (1 = enable, 0 = Stopped)
Bit
@PowerUp
Pin
Description
7
-
-
Reserved for W83176R-251
6
-
-
Reserved for W83176R-251
5
-
-
Reserved for W83176R-251
4
-
-
Reserved for W83176R-251
3
-
-
Reserved for W83176R-251
2
-
-
Reserved for W83176R-251
1
-
-
Reserved for W83176R-251
0
-
-
Reserved for W83176R-251
Publication Release Date:April. 2002
- 8 - Revision 1.0
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